1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class MachineRegisterInfo;
26 class AMDGPUTargetLowering : public TargetLowering {
28 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
33 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
36 /// \returns a RegisterSDNode representing Reg.
37 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
38 const TargetRegisterClass *RC,
39 unsigned Reg, EVT VT) const;
40 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
41 SelectionDAG &DAG) const;
43 bool isHWTrueValue(SDValue Op) const;
44 bool isHWFalseValue(SDValue Op) const;
46 void AnalyzeFormalArguments(CCState &State,
47 const SmallVectorImpl<ISD::InputArg> &Ins) const;
50 AMDGPUTargetLowering(TargetMachine &TM);
52 virtual bool isFAbsFree(EVT VT) const;
53 virtual bool isFNegFree(EVT VT) const;
54 virtual MVT getVectorIdxTy() const;
55 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
57 const SmallVectorImpl<ISD::OutputArg> &Outs,
58 const SmallVectorImpl<SDValue> &OutVals,
59 SDLoc DL, SelectionDAG &DAG) const;
60 virtual SDValue LowerCall(CallLoweringInfo &CLI,
61 SmallVectorImpl<SDValue> &InVals) const {
63 llvm_unreachable("Undefined function");
66 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
67 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
68 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
69 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
70 virtual const char* getTargetNodeName(unsigned Opcode) const;
72 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
76 // Functions defined in AMDILISelLowering.cpp
79 /// \brief Determine which of the bits specified in \p Mask are known to be
80 /// either zero or one and return them in the \p KnownZero and \p KnownOne
82 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
85 const SelectionDAG &DAG,
86 unsigned Depth = 0) const;
88 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
89 const CallInst &I, unsigned Intrinsic) const;
91 /// We want to mark f32/f64 floating point values as legal.
92 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
94 /// We don't want to shrink f64/f32 constants.
95 bool ShouldShrinkFPConstant(EVT VT) const;
98 void InitAMDILLowering();
99 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
109 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
110 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
114 namespace AMDGPUISD {
118 FIRST_NUMBER = ISD::BUILTIN_OP_END,
119 CALL, // Function call based on a single integer
120 UMUL, // 32bit unsigned multiplication
121 DIV_INF, // Divide with infinity returned on zero divisor
124 // End AMDIL ISD Opcodes
142 LAST_AMDGPU_ISD_NUMBER
146 } // End namespace AMDGPUISD
148 } // End namespace llvm
150 #endif // AMDGPUISELLOWERING_H