1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
27 class AMDGPUTargetLowering : public TargetLowering {
29 const AMDGPUSubtarget *Subtarget;
32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
35 SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 /// \brief Lower vector stores by merging the vector elements into an integer
41 /// of the same bitwidth.
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43 /// \brief Split a vector store into multiple scalar stores.
44 /// \returns The resulting chain.
46 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
57 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
58 static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
60 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
63 /// \returns a RegisterSDNode representing Reg.
64 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
65 const TargetRegisterClass *RC,
66 unsigned Reg, EVT VT) const;
67 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
68 SelectionDAG &DAG) const;
69 /// \brief Split a vector load into multiple scalar loads.
70 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
71 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
72 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
74 bool isHWTrueValue(SDValue Op) const;
75 bool isHWFalseValue(SDValue Op) const;
77 /// The SelectionDAGBuilder will automatically promote function arguments
78 /// with illegal types. However, this does not work for the AMDGPU targets
79 /// since the function arguments are stored in memory as these illegal types.
80 /// In order to handle this properly we need to get the origianl types sizes
81 /// from the LLVM IR Function and fixup the ISD:InputArg values before
82 /// passing them to AnalyzeFormalArguments()
83 void getOriginalFunctionArgs(SelectionDAG &DAG,
85 const SmallVectorImpl<ISD::InputArg> &Ins,
86 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
87 void AnalyzeFormalArguments(CCState &State,
88 const SmallVectorImpl<ISD::InputArg> &Ins) const;
91 AMDGPUTargetLowering(TargetMachine &TM);
93 bool isFAbsFree(EVT VT) const override;
94 bool isFNegFree(EVT VT) const override;
95 bool isTruncateFree(EVT Src, EVT Dest) const override;
96 bool isTruncateFree(Type *Src, Type *Dest) const override;
98 bool isZExtFree(Type *Src, Type *Dest) const override;
99 bool isZExtFree(EVT Src, EVT Dest) const override;
101 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
103 MVT getVectorIdxTy() const override;
104 bool isLoadBitCastBeneficial(EVT, EVT) const override;
105 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
107 const SmallVectorImpl<ISD::OutputArg> &Outs,
108 const SmallVectorImpl<SDValue> &OutVals,
109 SDLoc DL, SelectionDAG &DAG) const override;
110 SDValue LowerCall(CallLoweringInfo &CLI,
111 SmallVectorImpl<SDValue> &InVals) const override;
113 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
114 void ReplaceNodeResults(SDNode * N,
115 SmallVectorImpl<SDValue> &Results,
116 SelectionDAG &DAG) const override;
118 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
120 SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const;
121 const char* getTargetNodeName(unsigned Opcode) const override;
123 virtual SDNode *PostISelFolding(MachineSDNode *N,
124 SelectionDAG &DAG) const {
128 /// \brief Determine which of the bits specified in \p Mask are known to be
129 /// either zero or one and return them in the \p KnownZero and \p KnownOne
131 void computeKnownBitsForTargetNode(const SDValue Op,
134 const SelectionDAG &DAG,
135 unsigned Depth = 0) const override;
137 virtual unsigned ComputeNumSignBitsForTargetNode(
139 const SelectionDAG &DAG,
140 unsigned Depth = 0) const override;
142 // Functions defined in AMDILISelLowering.cpp
144 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
145 const CallInst &I, unsigned Intrinsic) const override;
147 /// We want to mark f32/f64 floating point values as legal.
148 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
150 /// We don't want to shrink f64/f32 constants.
151 bool ShouldShrinkFPConstant(EVT VT) const override;
153 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
156 void InitAMDILLowering();
158 SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
160 SelectionDAG &DAG) const;
161 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
165 namespace AMDGPUISD {
169 FIRST_NUMBER = ISD::BUILTIN_OP_END,
170 CALL, // Function call based on a single integer
171 UMUL, // 32bit unsigned multiplication
172 DIV_INF, // Divide with infinity returned on zero divisor
175 // End AMDIL ISD Opcodes
189 BFE_U32, // Extract range of bits with zero extension to 32-bits.
190 BFE_I32, // Extract range of bits with sign extension to 32-bits.
191 BFI, // (src0 & src1) | (~src0 & src2)
192 BFM, // Insert a range of bits into a 32-bit word.
208 // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
213 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
216 TBUFFER_STORE_FORMAT,
217 LAST_AMDGPU_ISD_NUMBER
221 } // End namespace AMDGPUISD
223 } // End namespace llvm
225 #endif // AMDGPUISELLOWERING_H