1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class MachineRegisterInfo;
25 class AMDGPUTargetLowering : public TargetLowering {
27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
32 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
35 /// \returns a RegisterSDNode representing Reg.
36 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
37 unsigned Reg, EVT VT) const;
39 bool isHWTrueValue(SDValue Op) const;
40 bool isHWFalseValue(SDValue Op) const;
43 AMDGPUTargetLowering(TargetMachine &TM);
45 virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
47 const SmallVectorImpl<ISD::InputArg> &Ins,
48 DebugLoc DL, SelectionDAG &DAG,
49 SmallVectorImpl<SDValue> &InVals) const;
51 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
53 const SmallVectorImpl<ISD::OutputArg> &Outs,
54 const SmallVectorImpl<SDValue> &OutVals,
55 DebugLoc DL, SelectionDAG &DAG) const;
56 virtual SDValue LowerCall(CallLoweringInfo &CLI,
57 SmallVectorImpl<SDValue> &InVals) const {
59 llvm_unreachable("Undefined function");
62 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
63 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
64 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
65 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
66 virtual const char* getTargetNodeName(unsigned Opcode) const;
68 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
72 // Functions defined in AMDILISelLowering.cpp
75 /// \brief Determine which of the bits specified in \p Mask are known to be
76 /// either zero or one and return them in the \p KnownZero and \p KnownOne
78 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
81 const SelectionDAG &DAG,
82 unsigned Depth = 0) const;
84 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
85 const CallInst &I, unsigned Intrinsic) const;
87 /// We want to mark f32/f64 floating point values as legal.
88 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
90 /// We don't want to shrink f64/f32 constants.
91 bool ShouldShrinkFPConstant(EVT VT) const;
94 void InitAMDILLowering();
95 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
105 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
106 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
110 namespace AMDGPUISD {
114 FIRST_NUMBER = ISD::BUILTIN_OP_END,
115 CALL, // Function call based on a single integer
116 UMUL, // 32bit unsigned multiplication
117 DIV_INF, // Divide with infinity returned on zero divisor
120 // End AMDIL ISD Opcodes
135 LAST_AMDGPU_ISD_NUMBER
139 } // End namespace AMDGPUISD
141 } // End namespace llvm
143 #endif // AMDGPUISELLOWERING_H