1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class MachineRegisterInfo;
26 class AMDGPUTargetLowering : public TargetLowering {
28 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
29 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
33 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
36 /// \returns a RegisterSDNode representing Reg.
37 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
38 const TargetRegisterClass *RC,
39 unsigned Reg, EVT VT) const;
40 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
41 SelectionDAG &DAG) const;
43 bool isHWTrueValue(SDValue Op) const;
44 bool isHWFalseValue(SDValue Op) const;
46 void AnalyzeFormalArguments(CCState &State,
47 const SmallVectorImpl<ISD::InputArg> &Ins) const;
50 AMDGPUTargetLowering(TargetMachine &TM);
52 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
54 const SmallVectorImpl<ISD::OutputArg> &Outs,
55 const SmallVectorImpl<SDValue> &OutVals,
56 SDLoc DL, SelectionDAG &DAG) const;
57 virtual SDValue LowerCall(CallLoweringInfo &CLI,
58 SmallVectorImpl<SDValue> &InVals) const {
60 llvm_unreachable("Undefined function");
63 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
64 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
65 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
66 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
67 virtual const char* getTargetNodeName(unsigned Opcode) const;
69 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
73 // Functions defined in AMDILISelLowering.cpp
76 /// \brief Determine which of the bits specified in \p Mask are known to be
77 /// either zero or one and return them in the \p KnownZero and \p KnownOne
79 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
82 const SelectionDAG &DAG,
83 unsigned Depth = 0) const;
85 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
86 const CallInst &I, unsigned Intrinsic) const;
88 /// We want to mark f32/f64 floating point values as legal.
89 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
91 /// We don't want to shrink f64/f32 constants.
92 bool ShouldShrinkFPConstant(EVT VT) const;
95 void InitAMDILLowering();
96 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
106 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
107 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
111 namespace AMDGPUISD {
115 FIRST_NUMBER = ISD::BUILTIN_OP_END,
116 CALL, // Function call based on a single integer
117 UMUL, // 32bit unsigned multiplication
118 DIV_INF, // Divide with infinity returned on zero divisor
121 // End AMDIL ISD Opcodes
139 LAST_AMDGPU_ISD_NUMBER
143 } // End namespace AMDGPUISD
145 } // End namespace llvm
147 #endif // AMDGPUISELLOWERING_H