1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
27 class AMDGPUTargetLowering : public TargetLowering {
29 const AMDGPUSubtarget *Subtarget;
32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
35 SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 /// \brief Lower vector stores by merging the vector elements into an integer
41 /// of the same bitwidth.
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43 /// \brief Split a vector store into multiple scalar stores.
44 /// \returns The resulting chain.
46 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
62 SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
64 SelectionDAG &DAG) const;
65 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
68 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
69 static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
71 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
74 /// \returns a RegisterSDNode representing Reg.
75 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
76 const TargetRegisterClass *RC,
77 unsigned Reg, EVT VT) const;
78 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
79 SelectionDAG &DAG) const;
80 /// \brief Split a vector load into multiple scalar loads.
81 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
82 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
85 bool isHWTrueValue(SDValue Op) const;
86 bool isHWFalseValue(SDValue Op) const;
88 /// The SelectionDAGBuilder will automatically promote function arguments
89 /// with illegal types. However, this does not work for the AMDGPU targets
90 /// since the function arguments are stored in memory as these illegal types.
91 /// In order to handle this properly we need to get the origianl types sizes
92 /// from the LLVM IR Function and fixup the ISD:InputArg values before
93 /// passing them to AnalyzeFormalArguments()
94 void getOriginalFunctionArgs(SelectionDAG &DAG,
96 const SmallVectorImpl<ISD::InputArg> &Ins,
97 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
98 void AnalyzeFormalArguments(CCState &State,
99 const SmallVectorImpl<ISD::InputArg> &Ins) const;
102 AMDGPUTargetLowering(TargetMachine &TM);
104 bool isFAbsFree(EVT VT) const override;
105 bool isFNegFree(EVT VT) const override;
106 bool isTruncateFree(EVT Src, EVT Dest) const override;
107 bool isTruncateFree(Type *Src, Type *Dest) const override;
109 bool isZExtFree(Type *Src, Type *Dest) const override;
110 bool isZExtFree(EVT Src, EVT Dest) const override;
112 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
114 MVT getVectorIdxTy() const override;
116 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
117 bool ShouldShrinkFPConstant(EVT VT) const override;
119 bool isLoadBitCastBeneficial(EVT, EVT) const override;
120 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
122 const SmallVectorImpl<ISD::OutputArg> &Outs,
123 const SmallVectorImpl<SDValue> &OutVals,
124 SDLoc DL, SelectionDAG &DAG) const override;
125 SDValue LowerCall(CallLoweringInfo &CLI,
126 SmallVectorImpl<SDValue> &InVals) const override;
128 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
129 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
130 void ReplaceNodeResults(SDNode * N,
131 SmallVectorImpl<SDValue> &Results,
132 SelectionDAG &DAG) const override;
134 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
136 SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const;
137 const char* getTargetNodeName(unsigned Opcode) const override;
139 virtual SDNode *PostISelFolding(MachineSDNode *N,
140 SelectionDAG &DAG) const {
144 /// \brief Determine which of the bits specified in \p Mask are known to be
145 /// either zero or one and return them in the \p KnownZero and \p KnownOne
147 void computeKnownBitsForTargetNode(const SDValue Op,
150 const SelectionDAG &DAG,
151 unsigned Depth = 0) const override;
153 virtual unsigned ComputeNumSignBitsForTargetNode(
155 const SelectionDAG &DAG,
156 unsigned Depth = 0) const override;
159 // Functions defined in AMDILISelLowering.cpp
160 void InitAMDILLowering();
161 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
164 namespace AMDGPUISD {
168 FIRST_NUMBER = ISD::BUILTIN_OP_END,
169 CALL, // Function call based on a single integer
170 UMUL, // 32bit unsigned multiplication
171 DIV_INF, // Divide with infinity returned on zero divisor
174 // End AMDIL ISD Opcodes
188 BFE_U32, // Extract range of bits with zero extension to 32-bits.
189 BFE_I32, // Extract range of bits with sign extension to 32-bits.
190 BFI, // (src0 & src1) | (~src0 & src2)
191 BFM, // Insert a range of bits into a 32-bit word.
192 BREV, // Reverse bits.
208 // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
213 /// This node is for VLIW targets and it is used to represent a vector
214 /// that is stored in consecutive registers with the same channel.
221 BUILD_VERTICAL_VECTOR,
222 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
225 TBUFFER_STORE_FORMAT,
226 LAST_AMDGPU_ISD_NUMBER
230 } // End namespace AMDGPUISD
232 } // End namespace llvm
234 #endif // AMDGPUISELLOWERING_H