1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implementation of the TargetInstrInfo class that is common to all
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #define GET_INSTRINFO_CTOR_DTOR
26 #define GET_INSTRINFO_NAMED_OPS
27 #define GET_INSTRMAP_INFO
28 #include "AMDGPUGenInstrInfo.inc"
30 // Pin the vtable to this file.
31 void AMDGPUInstrInfo::anchor() {}
33 AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
34 : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { }
36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
41 unsigned &SrcReg, unsigned &DstReg,
42 unsigned &SubIdx) const {
43 // TODO: Implement this function
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const {
49 // TODO: Implement this function
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
54 int &FrameIndex) const {
55 // TODO: Implement this function
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
60 const MachineMemOperand *&MMO,
61 int &FrameIndex) const {
62 // TODO: Implement this function
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
66 int &FrameIndex) const {
67 // TODO: Implement this function
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
71 int &FrameIndex) const {
72 // TODO: Implement this function
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
76 const MachineMemOperand *&MMO,
77 int &FrameIndex) const {
78 // TODO: Implement this function
83 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
84 MachineBasicBlock::iterator &MBBI,
85 LiveVariables *LV) const {
86 // TODO: Implement this function
89 bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter,
90 MachineBasicBlock &MBB) const {
91 while (iter != MBB.end()) {
92 switch (iter->getOpcode()) {
95 case AMDGPU::BRANCH_COND_i32:
96 case AMDGPU::BRANCH_COND_f32:
106 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator MI,
108 unsigned SrcReg, bool isKill,
110 const TargetRegisterClass *RC,
111 const TargetRegisterInfo *TRI) const {
112 llvm_unreachable("Not Implemented");
116 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator MI,
118 unsigned DestReg, int FrameIndex,
119 const TargetRegisterClass *RC,
120 const TargetRegisterInfo *TRI) const {
121 llvm_unreachable("Not Implemented");
124 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
125 MachineBasicBlock *MBB = MI->getParent();
126 int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
127 AMDGPU::OpName::addr);
128 // addr is a custom operand with multiple MI operands, and only the
129 // first MI operand is given a name.
130 int RegOpIdx = OffsetOpIdx + 1;
131 int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
132 AMDGPU::OpName::chan);
133 if (isRegisterLoad(*MI)) {
134 int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
135 AMDGPU::OpName::dst);
136 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
137 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
138 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
139 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
140 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
141 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
142 getIndirectAddrRegClass()->getRegister(Address));
144 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
147 } else if (isRegisterStore(*MI)) {
148 int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
149 AMDGPU::OpName::val);
150 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
151 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
152 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
153 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
154 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
155 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
156 buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
157 MI->getOperand(ValOpIdx).getReg());
159 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
160 calculateIndirectAddress(RegIndex, Channel),
173 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
175 const SmallVectorImpl<unsigned> &Ops,
176 int FrameIndex) const {
177 // TODO: Implement this function
181 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
183 const SmallVectorImpl<unsigned> &Ops,
184 MachineInstr *LoadMI) const {
185 // TODO: Implement this function
189 AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
190 const SmallVectorImpl<unsigned> &Ops) const {
191 // TODO: Implement this function
195 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
196 unsigned Reg, bool UnfoldLoad,
198 SmallVectorImpl<MachineInstr*> &NewMIs) const {
199 // TODO: Implement this function
204 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
205 SmallVectorImpl<SDNode*> &NewNodes) const {
206 // TODO: Implement this function
211 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
212 bool UnfoldLoad, bool UnfoldStore,
213 unsigned *LoadRegIndex) const {
214 // TODO: Implement this function
218 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
219 int64_t Offset1, int64_t Offset2,
220 unsigned NumLoads) const {
221 assert(Offset2 > Offset1
222 && "Second offset should be larger than first offset!");
223 // If we have less than 16 loads in a row, and the offsets are within 16,
224 // then schedule together.
225 // TODO: Make the loads schedule near if it fits in a cacheline
226 return (NumLoads < 16 && (Offset2 - Offset1) < 16);
230 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
232 // TODO: Implement this function
235 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
236 MachineBasicBlock::iterator MI) const {
237 // TODO: Implement this function
240 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
241 // TODO: Implement this function
245 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
246 const SmallVectorImpl<MachineOperand> &Pred2)
248 // TODO: Implement this function
252 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
253 std::vector<MachineOperand> &Pred) const {
254 // TODO: Implement this function
258 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
259 // TODO: Implement this function
260 return MI->getDesc().isPredicable();
264 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
265 // TODO: Implement this function
269 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
270 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
273 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
274 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
277 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
278 const MachineRegisterInfo &MRI = MF.getRegInfo();
279 const MachineFrameInfo *MFI = MF.getFrameInfo();
282 if (MFI->getNumObjects() == 0) {
286 if (MRI.livein_empty()) {
290 const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
291 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
292 LE = MRI.livein_end();
294 unsigned Reg = LI->first;
295 if (TargetRegisterInfo::isVirtualRegister(Reg) ||
296 !IndirectRC->contains(Reg))
301 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
303 if (IndirectRC->getRegister(RegIndex) == Reg)
306 Offset = std::max(Offset, (int)RegIndex);
312 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
314 const MachineFrameInfo *MFI = MF.getFrameInfo();
316 // Variable sized objects are not supported
317 assert(!MFI->hasVarSizedObjects());
319 if (MFI->getNumObjects() == 0) {
323 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
325 return getIndirectIndexBegin(MF) + Offset;
329 void AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
331 MachineRegisterInfo &MRI = MF.getRegInfo();
332 const AMDGPURegisterInfo & RI = getRegisterInfo();
334 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
335 MachineOperand &MO = MI.getOperand(i);
336 // Convert dst regclass to one that is supported by the ISA
337 if (MO.isReg() && MO.isDef()) {
338 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
339 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
340 const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);
344 MRI.setRegClass(MO.getReg(), newRegClass);
350 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
352 default: return Opcode;
353 case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
354 case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
355 case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
359 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
360 // header files, so we need to wrap it in a function that takes unsigned
364 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
365 return getMCOpcode(Opcode);