1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implementation of the TargetInstrInfo class that is common to all
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #define GET_INSTRINFO_CTOR_DTOR
26 #define GET_INSTRINFO_NAMED_OPS
27 #define GET_INSTRMAP_INFO
28 #include "AMDGPUGenInstrInfo.inc"
30 // Pin the vtable to this file.
31 void AMDGPUInstrInfo::anchor() {}
33 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st)
34 : AMDGPUGenInstrInfo(-1,-1), RI(st), ST(st) { }
36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
41 unsigned &SrcReg, unsigned &DstReg,
42 unsigned &SubIdx) const {
43 // TODO: Implement this function
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const {
49 // TODO: Implement this function
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
54 int &FrameIndex) const {
55 // TODO: Implement this function
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
60 const MachineMemOperand *&MMO,
61 int &FrameIndex) const {
62 // TODO: Implement this function
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
66 int &FrameIndex) const {
67 // TODO: Implement this function
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
71 int &FrameIndex) const {
72 // TODO: Implement this function
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
76 const MachineMemOperand *&MMO,
77 int &FrameIndex) const {
78 // TODO: Implement this function
83 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
84 MachineBasicBlock::iterator &MBBI,
85 LiveVariables *LV) const {
86 // TODO: Implement this function
91 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 unsigned SrcReg, bool isKill,
95 const TargetRegisterClass *RC,
96 const TargetRegisterInfo *TRI) const {
97 llvm_unreachable("Not Implemented");
101 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MI,
103 unsigned DestReg, int FrameIndex,
104 const TargetRegisterClass *RC,
105 const TargetRegisterInfo *TRI) const {
106 llvm_unreachable("Not Implemented");
109 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
110 MachineBasicBlock *MBB = MI->getParent();
111 int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
112 AMDGPU::OpName::addr);
113 // addr is a custom operand with multiple MI operands, and only the
114 // first MI operand is given a name.
115 int RegOpIdx = OffsetOpIdx + 1;
116 int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
117 AMDGPU::OpName::chan);
118 if (isRegisterLoad(*MI)) {
119 int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
120 AMDGPU::OpName::dst);
121 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
122 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
123 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
124 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
125 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
126 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
127 getIndirectAddrRegClass()->getRegister(Address));
129 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
132 } else if (isRegisterStore(*MI)) {
133 int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
134 AMDGPU::OpName::val);
135 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
136 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
137 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
138 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
139 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
140 buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
141 MI->getOperand(ValOpIdx).getReg());
143 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
144 calculateIndirectAddress(RegIndex, Channel),
157 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
159 const SmallVectorImpl<unsigned> &Ops,
160 int FrameIndex) const {
161 // TODO: Implement this function
165 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
167 const SmallVectorImpl<unsigned> &Ops,
168 MachineInstr *LoadMI) const {
169 // TODO: Implement this function
173 AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
174 const SmallVectorImpl<unsigned> &Ops) const {
175 // TODO: Implement this function
179 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
180 unsigned Reg, bool UnfoldLoad,
182 SmallVectorImpl<MachineInstr*> &NewMIs) const {
183 // TODO: Implement this function
188 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
189 SmallVectorImpl<SDNode*> &NewNodes) const {
190 // TODO: Implement this function
195 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
196 bool UnfoldLoad, bool UnfoldStore,
197 unsigned *LoadRegIndex) const {
198 // TODO: Implement this function
202 bool AMDGPUInstrInfo::enableClusterLoads() const {
206 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
207 // the first 16 loads will be interleaved with the stores, and the next 16 will
208 // be clustered as expected. It should really split into 2 16 store batches.
210 // Loads are clustered until this returns false, rather than trying to schedule
211 // groups of stores. This also means we have to deal with saying different
212 // address space loads should be clustered, and ones which might cause bank
215 // This might be deprecated so it might not be worth that much effort to fix.
216 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
217 int64_t Offset0, int64_t Offset1,
218 unsigned NumLoads) const {
219 assert(Offset1 > Offset0 &&
220 "Second offset should be larger than first offset!");
221 // If we have less than 16 loads in a row, and the offsets are within 64
222 // bytes, then schedule together.
224 // A cacheline is 64 bytes (for global memory).
225 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
229 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
231 // TODO: Implement this function
234 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
235 MachineBasicBlock::iterator MI) const {
236 // TODO: Implement this function
239 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
240 // TODO: Implement this function
244 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
245 const SmallVectorImpl<MachineOperand> &Pred2)
247 // TODO: Implement this function
251 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
252 std::vector<MachineOperand> &Pred) const {
253 // TODO: Implement this function
257 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
258 // TODO: Implement this function
259 return MI->getDesc().isPredicable();
263 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
264 // TODO: Implement this function
268 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
269 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
272 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
273 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
276 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
277 const MachineRegisterInfo &MRI = MF.getRegInfo();
278 const MachineFrameInfo *MFI = MF.getFrameInfo();
281 if (MFI->getNumObjects() == 0) {
285 if (MRI.livein_empty()) {
289 const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
290 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
291 LE = MRI.livein_end();
293 unsigned Reg = LI->first;
294 if (TargetRegisterInfo::isVirtualRegister(Reg) ||
295 !IndirectRC->contains(Reg))
300 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
302 if (IndirectRC->getRegister(RegIndex) == Reg)
305 Offset = std::max(Offset, (int)RegIndex);
311 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
313 const MachineFrameInfo *MFI = MF.getFrameInfo();
315 // Variable sized objects are not supported
316 assert(!MFI->hasVarSizedObjects());
318 if (MFI->getNumObjects() == 0) {
322 Offset = MF.getSubtarget().getFrameLowering()->getFrameIndexOffset(MF, -1);
324 return getIndirectIndexBegin(MF) + Offset;
327 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
329 default: return Opcode;
330 case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
331 case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
332 case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
336 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
337 // header files, so we need to wrap it in a function that takes unsigned
341 static int getMCOpcode(uint16_t Opcode, unsigned Gen) {
342 return getMCOpcodeGen(Opcode, (enum Subtarget)Gen);
347 // This must be kept in sync with the SISubtarget class in SIInstrInfo.td
353 enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) {
357 case AMDGPUSubtarget::VOLCANIC_ISLANDS:
362 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
363 int MCOp = AMDGPU::getMCOpcode(Opcode,
364 AMDGPUSubtargetToSISubtarget(RI.ST.getGeneration()));
366 // -1 means that Opcode is already a native instruction.
370 // (uint16_t)-1 means that Opcode is a pseudo instruction that has
371 // no encoding in the given subtarget generation.
372 if (MCOp == (uint16_t)-1)