1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implementation of the TargetInstrInfo class that is common to all
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #define GET_INSTRINFO_CTOR_DTOR
24 #define GET_INSTRINFO_NAMED_OPS
25 #define GET_INSTRMAP_INFO
26 #include "AMDGPUGenInstrInfo.inc"
31 // Pin the vtable to this file.
32 void AMDGPUInstrInfo::anchor() {}
34 AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
35 : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { }
37 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
41 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
42 unsigned &SrcReg, unsigned &DstReg,
43 unsigned &SubIdx) const {
44 // TODO: Implement this function
48 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
49 int &FrameIndex) const {
50 // TODO: Implement this function
54 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
55 int &FrameIndex) const {
56 // TODO: Implement this function
60 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
61 const MachineMemOperand *&MMO,
62 int &FrameIndex) const {
63 // TODO: Implement this function
66 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
67 int &FrameIndex) const {
68 // TODO: Implement this function
71 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
72 int &FrameIndex) const {
73 // TODO: Implement this function
76 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
77 const MachineMemOperand *&MMO,
78 int &FrameIndex) const {
79 // TODO: Implement this function
84 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
85 MachineBasicBlock::iterator &MBBI,
86 LiveVariables *LV) const {
87 // TODO: Implement this function
90 bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter,
91 MachineBasicBlock &MBB) const {
92 while (iter != MBB.end()) {
93 switch (iter->getOpcode()) {
96 case AMDGPU::BRANCH_COND_i32:
97 case AMDGPU::BRANCH_COND_f32:
107 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator MI,
109 unsigned SrcReg, bool isKill,
111 const TargetRegisterClass *RC,
112 const TargetRegisterInfo *TRI) const {
113 llvm_unreachable("Not Implemented");
117 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator MI,
119 unsigned DestReg, int FrameIndex,
120 const TargetRegisterClass *RC,
121 const TargetRegisterInfo *TRI) const {
122 llvm_unreachable("Not Implemented");
125 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
126 MachineBasicBlock *MBB = MI->getParent();
128 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::addr);
129 // addr is a custom operand with multiple MI operands, and only the
130 // first MI operand is given a name.
131 int RegOpIdx = OffsetOpIdx + 1;
133 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::chan);
135 if (isRegisterLoad(*MI)) {
137 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
138 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
139 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
140 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
141 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
142 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
143 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
144 getIndirectAddrRegClass()->getRegister(Address));
146 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
149 } else if (isRegisterStore(*MI)) {
151 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::val);
152 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
153 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
154 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
155 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
156 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
157 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
158 buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
159 MI->getOperand(ValOpIdx).getReg());
161 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
162 calculateIndirectAddress(RegIndex, Channel),
175 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
177 const SmallVectorImpl<unsigned> &Ops,
178 int FrameIndex) const {
179 // TODO: Implement this function
183 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
185 const SmallVectorImpl<unsigned> &Ops,
186 MachineInstr *LoadMI) const {
187 // TODO: Implement this function
191 AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
192 const SmallVectorImpl<unsigned> &Ops) const {
193 // TODO: Implement this function
197 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
198 unsigned Reg, bool UnfoldLoad,
200 SmallVectorImpl<MachineInstr*> &NewMIs) const {
201 // TODO: Implement this function
206 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
207 SmallVectorImpl<SDNode*> &NewNodes) const {
208 // TODO: Implement this function
213 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
214 bool UnfoldLoad, bool UnfoldStore,
215 unsigned *LoadRegIndex) const {
216 // TODO: Implement this function
220 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
221 int64_t Offset1, int64_t Offset2,
222 unsigned NumLoads) const {
223 assert(Offset2 > Offset1
224 && "Second offset should be larger than first offset!");
225 // If we have less than 16 loads in a row, and the offsets are within 16,
226 // then schedule together.
227 // TODO: Make the loads schedule near if it fits in a cacheline
228 return (NumLoads < 16 && (Offset2 - Offset1) < 16);
232 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
234 // TODO: Implement this function
237 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
238 MachineBasicBlock::iterator MI) const {
239 // TODO: Implement this function
242 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
243 // TODO: Implement this function
247 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
248 const SmallVectorImpl<MachineOperand> &Pred2)
250 // TODO: Implement this function
254 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
255 std::vector<MachineOperand> &Pred) const {
256 // TODO: Implement this function
260 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
261 // TODO: Implement this function
262 return MI->getDesc().isPredicable();
266 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
267 // TODO: Implement this function
271 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
272 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
275 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
276 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
279 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
280 const MachineRegisterInfo &MRI = MF.getRegInfo();
281 const MachineFrameInfo *MFI = MF.getFrameInfo();
284 if (MFI->getNumObjects() == 0) {
288 if (MRI.livein_empty()) {
292 const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
293 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
294 LE = MRI.livein_end();
296 unsigned Reg = LI->first;
297 if (TargetRegisterInfo::isVirtualRegister(Reg) ||
298 !IndirectRC->contains(Reg))
303 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
305 if (IndirectRC->getRegister(RegIndex) == Reg)
308 Offset = std::max(Offset, (int)RegIndex);
314 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
316 const MachineFrameInfo *MFI = MF.getFrameInfo();
318 // Variable sized objects are not supported
319 assert(!MFI->hasVarSizedObjects());
321 if (MFI->getNumObjects() == 0) {
325 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
327 return getIndirectIndexBegin(MF) + Offset;
331 void AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
333 MachineRegisterInfo &MRI = MF.getRegInfo();
334 const AMDGPURegisterInfo & RI = getRegisterInfo();
336 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
337 MachineOperand &MO = MI.getOperand(i);
338 // Convert dst regclass to one that is supported by the ISA
339 if (MO.isReg() && MO.isDef()) {
340 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
341 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
342 const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);
346 MRI.setRegClass(MO.getReg(), newRegClass);
352 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
354 default: return Opcode;
355 case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
356 case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
357 case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);