1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implementation of the TargetInstrInfo class that is common to all
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #define GET_INSTRINFO_CTOR_DTOR
26 #define GET_INSTRINFO_NAMED_OPS
27 #define GET_INSTRMAP_INFO
28 #include "AMDGPUGenInstrInfo.inc"
30 // Pin the vtable to this file.
31 void AMDGPUInstrInfo::anchor() {}
33 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st)
34 : AMDGPUGenInstrInfo(-1,-1), RI(st), ST(st) { }
36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
41 unsigned &SrcReg, unsigned &DstReg,
42 unsigned &SubIdx) const {
43 // TODO: Implement this function
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const {
49 // TODO: Implement this function
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
54 int &FrameIndex) const {
55 // TODO: Implement this function
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
60 const MachineMemOperand *&MMO,
61 int &FrameIndex) const {
62 // TODO: Implement this function
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
66 int &FrameIndex) const {
67 // TODO: Implement this function
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
71 int &FrameIndex) const {
72 // TODO: Implement this function
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
76 const MachineMemOperand *&MMO,
77 int &FrameIndex) const {
78 // TODO: Implement this function
83 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
84 MachineBasicBlock::iterator &MBBI,
85 LiveVariables *LV) const {
86 // TODO: Implement this function
89 bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter,
90 MachineBasicBlock &MBB) const {
91 while (iter != MBB.end()) {
92 switch (iter->getOpcode()) {
95 case AMDGPU::BRANCH_COND_i32:
96 case AMDGPU::BRANCH_COND_f32:
106 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator MI,
108 unsigned SrcReg, bool isKill,
110 const TargetRegisterClass *RC,
111 const TargetRegisterInfo *TRI) const {
112 llvm_unreachable("Not Implemented");
116 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator MI,
118 unsigned DestReg, int FrameIndex,
119 const TargetRegisterClass *RC,
120 const TargetRegisterInfo *TRI) const {
121 llvm_unreachable("Not Implemented");
124 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
125 MachineBasicBlock *MBB = MI->getParent();
126 int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
127 AMDGPU::OpName::addr);
128 // addr is a custom operand with multiple MI operands, and only the
129 // first MI operand is given a name.
130 int RegOpIdx = OffsetOpIdx + 1;
131 int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
132 AMDGPU::OpName::chan);
133 if (isRegisterLoad(*MI)) {
134 int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
135 AMDGPU::OpName::dst);
136 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
137 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
138 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
139 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
140 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
141 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
142 getIndirectAddrRegClass()->getRegister(Address));
144 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
147 } else if (isRegisterStore(*MI)) {
148 int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
149 AMDGPU::OpName::val);
150 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
151 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
152 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
153 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
154 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
155 buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
156 MI->getOperand(ValOpIdx).getReg());
158 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
159 calculateIndirectAddress(RegIndex, Channel),
172 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
174 const SmallVectorImpl<unsigned> &Ops,
175 int FrameIndex) const {
176 // TODO: Implement this function
180 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
182 const SmallVectorImpl<unsigned> &Ops,
183 MachineInstr *LoadMI) const {
184 // TODO: Implement this function
188 AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
189 const SmallVectorImpl<unsigned> &Ops) const {
190 // TODO: Implement this function
194 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
195 unsigned Reg, bool UnfoldLoad,
197 SmallVectorImpl<MachineInstr*> &NewMIs) const {
198 // TODO: Implement this function
203 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
204 SmallVectorImpl<SDNode*> &NewNodes) const {
205 // TODO: Implement this function
210 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
211 bool UnfoldLoad, bool UnfoldStore,
212 unsigned *LoadRegIndex) const {
213 // TODO: Implement this function
217 bool AMDGPUInstrInfo::enableClusterLoads() const {
221 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
222 // the first 16 loads will be interleaved with the stores, and the next 16 will
223 // be clustered as expected. It should really split into 2 16 store batches.
225 // Loads are clustered until this returns false, rather than trying to schedule
226 // groups of stores. This also means we have to deal with saying different
227 // address space loads should be clustered, and ones which might cause bank
230 // This might be deprecated so it might not be worth that much effort to fix.
231 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
232 int64_t Offset0, int64_t Offset1,
233 unsigned NumLoads) const {
234 assert(Offset1 > Offset0 &&
235 "Second offset should be larger than first offset!");
236 // If we have less than 16 loads in a row, and the offsets are within 64
237 // bytes, then schedule together.
239 // A cacheline is 64 bytes (for global memory).
240 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
244 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
246 // TODO: Implement this function
249 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
250 MachineBasicBlock::iterator MI) const {
251 // TODO: Implement this function
254 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
255 // TODO: Implement this function
259 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
260 const SmallVectorImpl<MachineOperand> &Pred2)
262 // TODO: Implement this function
266 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
267 std::vector<MachineOperand> &Pred) const {
268 // TODO: Implement this function
272 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
273 // TODO: Implement this function
274 return MI->getDesc().isPredicable();
278 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
279 // TODO: Implement this function
283 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
284 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
287 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
288 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
291 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
292 const MachineRegisterInfo &MRI = MF.getRegInfo();
293 const MachineFrameInfo *MFI = MF.getFrameInfo();
296 if (MFI->getNumObjects() == 0) {
300 if (MRI.livein_empty()) {
304 const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
305 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
306 LE = MRI.livein_end();
308 unsigned Reg = LI->first;
309 if (TargetRegisterInfo::isVirtualRegister(Reg) ||
310 !IndirectRC->contains(Reg))
315 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
317 if (IndirectRC->getRegister(RegIndex) == Reg)
320 Offset = std::max(Offset, (int)RegIndex);
326 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
328 const MachineFrameInfo *MFI = MF.getFrameInfo();
330 // Variable sized objects are not supported
331 assert(!MFI->hasVarSizedObjects());
333 if (MFI->getNumObjects() == 0) {
337 Offset = MF.getTarget()
340 ->getFrameIndexOffset(MF, -1);
342 return getIndirectIndexBegin(MF) + Offset;
345 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
347 default: return Opcode;
348 case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
349 case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
350 case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
354 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
355 // header files, so we need to wrap it in a function that takes unsigned
359 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
360 return getMCOpcode(Opcode);