lib/Target/R600/AMDGPUInstrInfo.h

   1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief Contains the definition of a TargetInstrInfo class that is common
  12 /// to all AMD GPUs.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef AMDGPUINSTRUCTIONINFO_H
  17 #define AMDGPUINSTRUCTIONINFO_H
  18
  19 #include "AMDGPURegisterInfo.h"
  20 #include "AMDGPUInstrInfo.h"
  21 #include "llvm/Target/TargetInstrInfo.h"
  22
  23 #include <map>
  24
  25 #define GET_INSTRINFO_HEADER
  26 #define GET_INSTRINFO_ENUM
  27 #include "AMDGPUGenInstrInfo.inc"
  28
  29 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
  30 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
  31 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
  32 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
  33
  34 namespace llvm {
  35
  36 class AMDGPUTargetMachine;
  37 class MachineFunction;
  38 class MachineInstr;
  39 class MachineInstrBuilder;
  40
  41 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
  42 private:
  43   const AMDGPURegisterInfo RI;
  44   TargetMachine &TM;
  45   bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
  46                           MachineBasicBlock &MBB) const;
  47 public:
  48   explicit AMDGPUInstrInfo(TargetMachine &tm);
  49
  50   virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
  51
  52   bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
  53                              unsigned &DstReg, unsigned &SubIdx) const;
  54
  55   unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  56   unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
  57                                      int &FrameIndex) const;
  58   bool hasLoadFromStackSlot(const MachineInstr *MI,
  59                             const MachineMemOperand *&MMO,
  60                             int &FrameIndex) const;
  61   unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  62   unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
  63                                       int &FrameIndex) const;
  64   bool hasStoreFromStackSlot(const MachineInstr *MI,
  65                              const MachineMemOperand *&MMO,
  66                              int &FrameIndex) const;
  67
  68   MachineInstr *
  69   convertToThreeAddress(MachineFunction::iterator &MFI,
  70                         MachineBasicBlock::iterator &MBBI,
  71                         LiveVariables *LV) const;
  72
  73
  74   virtual void copyPhysReg(MachineBasicBlock &MBB,
  75                            MachineBasicBlock::iterator MI, DebugLoc DL,
  76                            unsigned DestReg, unsigned SrcReg,
  77                            bool KillSrc) const = 0;
  78
  79   void storeRegToStackSlot(MachineBasicBlock &MBB,
  80                            MachineBasicBlock::iterator MI,
  81                            unsigned SrcReg, bool isKill, int FrameIndex,
  82                            const TargetRegisterClass *RC,
  83                            const TargetRegisterInfo *TRI) const;
  84   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  85                             MachineBasicBlock::iterator MI,
  86                             unsigned DestReg, int FrameIndex,
  87                             const TargetRegisterClass *RC,
  88                             const TargetRegisterInfo *TRI) const;
  89
  90 protected:
  91   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
  92                                       MachineInstr *MI,
  93                                       const SmallVectorImpl<unsigned> &Ops,
  94                                       int FrameIndex) const;
  95   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
  96                                       MachineInstr *MI,
  97                                       const SmallVectorImpl<unsigned> &Ops,
  98                                       MachineInstr *LoadMI) const;
  99 public:
 100   bool canFoldMemoryOperand(const MachineInstr *MI,
 101                             const SmallVectorImpl<unsigned> &Ops) const;
 102   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
 103                            unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
 104                            SmallVectorImpl<MachineInstr *> &NewMIs) const;
 105   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
 106                            SmallVectorImpl<SDNode *> &NewNodes) const;
 107   unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
 108                                       bool UnfoldLoad, bool UnfoldStore,
 109                                       unsigned *LoadRegIndex = 0) const;
 110   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
 111                                int64_t Offset1, int64_t Offset2,
 112                                unsigned NumLoads) const;
 113
 114   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 115   void insertNoop(MachineBasicBlock &MBB,
 116                   MachineBasicBlock::iterator MI) const;
 117   bool isPredicated(const MachineInstr *MI) const;
 118   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
 119                          const SmallVectorImpl<MachineOperand> &Pred2) const;
 120   bool DefinesPredicate(MachineInstr *MI,
 121                         std::vector<MachineOperand> &Pred) const;
 122   bool isPredicable(MachineInstr *MI) const;
 123   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
 124
 125   // Helper functions that check the opcode for status information
 126   bool isLoadInst(llvm::MachineInstr *MI) const;
 127   bool isExtLoadInst(llvm::MachineInstr *MI) const;
 128   bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
 129   bool isSExtLoadInst(llvm::MachineInstr *MI) const;
 130   bool isZExtLoadInst(llvm::MachineInstr *MI) const;
 131   bool isAExtLoadInst(llvm::MachineInstr *MI) const;
 132   bool isStoreInst(llvm::MachineInstr *MI) const;
 133   bool isTruncStoreInst(llvm::MachineInstr *MI) const;
 134
 135   virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg,
 136                                        int64_t Imm) const = 0;
 137   virtual unsigned getIEQOpcode() const = 0;
 138   virtual bool isMov(unsigned opcode) const = 0;
 139
 140   /// \brief Convert the AMDIL MachineInstr to a supported ISA
 141   /// MachineInstr
 142   virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
 143     DebugLoc DL) const;
 144
 145 };
 146
 147 } // End llvm namespace
 148
 149 #endif // AMDGPUINSTRINFO_H