1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUINSTRUCTIONINFO_H
17 #define AMDGPUINSTRUCTIONINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #define GET_INSTRINFO_ENUM
26 #define GET_INSTRINFO_OPERAND_ENUM
27 #include "AMDGPUGenInstrInfo.inc"
29 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
30 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
31 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
32 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
36 class AMDGPUTargetMachine;
37 class MachineFunction;
39 class MachineInstrBuilder;
41 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
43 const AMDGPURegisterInfo RI;
44 bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
45 MachineBasicBlock &MBB) const;
46 virtual void anchor();
50 explicit AMDGPUInstrInfo(TargetMachine &tm);
52 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
54 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
55 unsigned &DstReg, unsigned &SubIdx) const override;
57 unsigned isLoadFromStackSlot(const MachineInstr *MI,
58 int &FrameIndex) const override;
59 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
60 int &FrameIndex) const override;
61 bool hasLoadFromStackSlot(const MachineInstr *MI,
62 const MachineMemOperand *&MMO,
63 int &FrameIndex) const override;
64 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
65 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
66 int &FrameIndex) const;
67 bool hasStoreFromStackSlot(const MachineInstr *MI,
68 const MachineMemOperand *&MMO,
69 int &FrameIndex) const;
72 convertToThreeAddress(MachineFunction::iterator &MFI,
73 MachineBasicBlock::iterator &MBBI,
74 LiveVariables *LV) const override;
77 virtual void copyPhysReg(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator MI, DebugLoc DL,
79 unsigned DestReg, unsigned SrcReg,
80 bool KillSrc) const = 0;
82 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
84 void storeRegToStackSlot(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MI,
86 unsigned SrcReg, bool isKill, int FrameIndex,
87 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const override;
89 void loadRegFromStackSlot(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MI,
91 unsigned DestReg, int FrameIndex,
92 const TargetRegisterClass *RC,
93 const TargetRegisterInfo *TRI) const override;
96 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
98 const SmallVectorImpl<unsigned> &Ops,
99 int FrameIndex) const override;
100 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
102 const SmallVectorImpl<unsigned> &Ops,
103 MachineInstr *LoadMI) const override;
104 /// \returns the smallest register index that will be accessed by an indirect
105 /// read or write or -1 if indirect addressing is not used by this program.
106 int getIndirectIndexBegin(const MachineFunction &MF) const;
108 /// \returns the largest register index that will be accessed by an indirect
109 /// read or write or -1 if indirect addressing is not used by this program.
110 int getIndirectIndexEnd(const MachineFunction &MF) const;
113 bool canFoldMemoryOperand(const MachineInstr *MI,
114 const SmallVectorImpl<unsigned> &Ops) const override;
115 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
116 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
117 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
118 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
119 SmallVectorImpl<SDNode *> &NewNodes) const override;
120 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
121 bool UnfoldLoad, bool UnfoldStore,
122 unsigned *LoadRegIndex = nullptr) const override;
123 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
124 int64_t Offset1, int64_t Offset2,
125 unsigned NumLoads) const override;
128 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
129 void insertNoop(MachineBasicBlock &MBB,
130 MachineBasicBlock::iterator MI) const override;
131 bool isPredicated(const MachineInstr *MI) const override;
132 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
133 const SmallVectorImpl<MachineOperand> &Pred2) const override;
134 bool DefinesPredicate(MachineInstr *MI,
135 std::vector<MachineOperand> &Pred) const override;
136 bool isPredicable(MachineInstr *MI) const override;
137 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
139 // Helper functions that check the opcode for status information
140 bool isLoadInst(llvm::MachineInstr *MI) const;
141 bool isExtLoadInst(llvm::MachineInstr *MI) const;
142 bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
143 bool isSExtLoadInst(llvm::MachineInstr *MI) const;
144 bool isZExtLoadInst(llvm::MachineInstr *MI) const;
145 bool isAExtLoadInst(llvm::MachineInstr *MI) const;
146 bool isStoreInst(llvm::MachineInstr *MI) const;
147 bool isTruncStoreInst(llvm::MachineInstr *MI) const;
148 bool isRegisterStore(const MachineInstr &MI) const;
149 bool isRegisterLoad(const MachineInstr &MI) const;
151 //===---------------------------------------------------------------------===//
152 // Pure virtual funtions to be implemented by sub-classes.
153 //===---------------------------------------------------------------------===//
155 virtual unsigned getIEQOpcode() const = 0;
156 virtual bool isMov(unsigned opcode) const = 0;
158 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and
161 /// We model indirect addressing using a virtual address space that can be
162 /// accesed with loads and stores. The "Indirect Address" is the memory
163 /// address in this virtual address space that maps to the given \p RegIndex
165 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
166 unsigned Channel) const = 0;
168 /// \returns The register class to be used for loading and storing values
169 /// from an "Indirect Address" .
170 virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
172 /// \brief Build instruction(s) for an indirect register write.
174 /// \returns The instruction that performs the indirect register write
175 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
176 MachineBasicBlock::iterator I,
177 unsigned ValueReg, unsigned Address,
178 unsigned OffsetReg) const = 0;
180 /// \brief Build instruction(s) for an indirect register read.
182 /// \returns The instruction that performs the indirect register read
183 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
184 MachineBasicBlock::iterator I,
185 unsigned ValueReg, unsigned Address,
186 unsigned OffsetReg) const = 0;
189 /// \brief Convert the AMDIL MachineInstr to a supported ISA
191 void convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const;
193 /// \brief Build a MOV instruction.
194 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
195 MachineBasicBlock::iterator I,
196 unsigned DstReg, unsigned SrcReg) const = 0;
198 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
199 /// equivalent opcode that writes \p Channels Channels.
200 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
205 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
206 } // End namespace AMDGPU
208 } // End llvm namespace
210 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
211 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
213 #endif // AMDGPUINSTRINFO_H