1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
19 #include "AMDGPURegisterInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #define GET_INSTRINFO_ENUM
25 #define GET_INSTRINFO_OPERAND_ENUM
26 #include "AMDGPUGenInstrInfo.inc"
28 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
29 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
30 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
31 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
35 class AMDGPUSubtarget;
36 class MachineFunction;
38 class MachineInstrBuilder;
40 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
42 const AMDGPURegisterInfo RI;
43 bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
44 MachineBasicBlock &MBB) const;
45 virtual void anchor();
47 const AMDGPUSubtarget &ST;
49 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
51 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
53 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned &DstReg, unsigned &SubIdx) const override;
56 unsigned isLoadFromStackSlot(const MachineInstr *MI,
57 int &FrameIndex) const override;
58 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
59 int &FrameIndex) const override;
60 bool hasLoadFromStackSlot(const MachineInstr *MI,
61 const MachineMemOperand *&MMO,
62 int &FrameIndex) const override;
63 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
64 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
65 int &FrameIndex) const;
66 bool hasStoreFromStackSlot(const MachineInstr *MI,
67 const MachineMemOperand *&MMO,
68 int &FrameIndex) const;
71 convertToThreeAddress(MachineFunction::iterator &MFI,
72 MachineBasicBlock::iterator &MBBI,
73 LiveVariables *LV) const override;
76 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
78 void storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 unsigned SrcReg, bool isKill, int FrameIndex,
81 const TargetRegisterClass *RC,
82 const TargetRegisterInfo *TRI) const override;
83 void loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned DestReg, int FrameIndex,
86 const TargetRegisterClass *RC,
87 const TargetRegisterInfo *TRI) const override;
90 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
92 const SmallVectorImpl<unsigned> &Ops,
93 int FrameIndex) const override;
94 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
96 const SmallVectorImpl<unsigned> &Ops,
97 MachineInstr *LoadMI) const override;
99 /// \returns the smallest register index that will be accessed by an indirect
100 /// read or write or -1 if indirect addressing is not used by this program.
101 int getIndirectIndexBegin(const MachineFunction &MF) const;
103 /// \returns the largest register index that will be accessed by an indirect
104 /// read or write or -1 if indirect addressing is not used by this program.
105 int getIndirectIndexEnd(const MachineFunction &MF) const;
107 bool canFoldMemoryOperand(const MachineInstr *MI,
108 const SmallVectorImpl<unsigned> &Ops) const override;
109 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
110 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
111 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
112 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
113 SmallVectorImpl<SDNode *> &NewNodes) const override;
114 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
115 bool UnfoldLoad, bool UnfoldStore,
116 unsigned *LoadRegIndex = nullptr) const override;
118 bool enableClusterLoads() const override;
120 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
121 int64_t Offset1, int64_t Offset2,
122 unsigned NumLoads) const override;
125 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
126 void insertNoop(MachineBasicBlock &MBB,
127 MachineBasicBlock::iterator MI) const override;
128 bool isPredicated(const MachineInstr *MI) const override;
129 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
130 const SmallVectorImpl<MachineOperand> &Pred2) const override;
131 bool DefinesPredicate(MachineInstr *MI,
132 std::vector<MachineOperand> &Pred) const override;
133 bool isPredicable(MachineInstr *MI) const override;
134 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
136 // Helper functions that check the opcode for status information
137 bool isRegisterStore(const MachineInstr &MI) const;
138 bool isRegisterLoad(const MachineInstr &MI) const;
140 //===---------------------------------------------------------------------===//
141 // Pure virtual funtions to be implemented by sub-classes.
142 //===---------------------------------------------------------------------===//
144 virtual bool isMov(unsigned opcode) const = 0;
146 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and
149 /// We model indirect addressing using a virtual address space that can be
150 /// accesed with loads and stores. The "Indirect Address" is the memory
151 /// address in this virtual address space that maps to the given \p RegIndex
153 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
154 unsigned Channel) const = 0;
156 /// \returns The register class to be used for loading and storing values
157 /// from an "Indirect Address" .
158 virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
160 /// \brief Build instruction(s) for an indirect register write.
162 /// \returns The instruction that performs the indirect register write
163 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
164 MachineBasicBlock::iterator I,
165 unsigned ValueReg, unsigned Address,
166 unsigned OffsetReg) const = 0;
168 /// \brief Build instruction(s) for an indirect register read.
170 /// \returns The instruction that performs the indirect register read
171 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
172 MachineBasicBlock::iterator I,
173 unsigned ValueReg, unsigned Address,
174 unsigned OffsetReg) const = 0;
176 /// \brief Build a MOV instruction.
177 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
178 MachineBasicBlock::iterator I,
179 unsigned DstReg, unsigned SrcReg) const = 0;
181 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
182 /// equivalent opcode that writes \p Channels Channels.
183 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
188 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
189 } // End namespace AMDGPU
191 } // End llvm namespace
193 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
194 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)