1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUINSTRINFO_H
17 #define AMDGPUINSTRINFO_H
19 #include "AMDGPURegisterInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #define GET_INSTRINFO_ENUM
25 #define GET_INSTRINFO_OPERAND_ENUM
26 #include "AMDGPUGenInstrInfo.inc"
28 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
29 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
30 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
31 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
35 class AMDGPUSubtarget;
36 class MachineFunction;
38 class MachineInstrBuilder;
40 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
42 const AMDGPURegisterInfo RI;
43 bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
44 MachineBasicBlock &MBB) const;
45 virtual void anchor();
47 const AMDGPUSubtarget &ST;
49 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
51 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
53 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned &DstReg, unsigned &SubIdx) const override;
56 unsigned isLoadFromStackSlot(const MachineInstr *MI,
57 int &FrameIndex) const override;
58 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
59 int &FrameIndex) const override;
60 bool hasLoadFromStackSlot(const MachineInstr *MI,
61 const MachineMemOperand *&MMO,
62 int &FrameIndex) const override;
63 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
64 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
65 int &FrameIndex) const;
66 bool hasStoreFromStackSlot(const MachineInstr *MI,
67 const MachineMemOperand *&MMO,
68 int &FrameIndex) const;
71 convertToThreeAddress(MachineFunction::iterator &MFI,
72 MachineBasicBlock::iterator &MBBI,
73 LiveVariables *LV) const override;
76 virtual void copyPhysReg(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator MI, DebugLoc DL,
78 unsigned DestReg, unsigned SrcReg,
79 bool KillSrc) const = 0;
81 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
83 void storeRegToStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned SrcReg, bool isKill, int FrameIndex,
86 const TargetRegisterClass *RC,
87 const TargetRegisterInfo *TRI) const override;
88 void loadRegFromStackSlot(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MI,
90 unsigned DestReg, int FrameIndex,
91 const TargetRegisterClass *RC,
92 const TargetRegisterInfo *TRI) const override;
95 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
97 const SmallVectorImpl<unsigned> &Ops,
98 int FrameIndex) const override;
99 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
101 const SmallVectorImpl<unsigned> &Ops,
102 MachineInstr *LoadMI) const override;
103 /// \returns the smallest register index that will be accessed by an indirect
104 /// read or write or -1 if indirect addressing is not used by this program.
105 int getIndirectIndexBegin(const MachineFunction &MF) const;
107 /// \returns the largest register index that will be accessed by an indirect
108 /// read or write or -1 if indirect addressing is not used by this program.
109 int getIndirectIndexEnd(const MachineFunction &MF) const;
112 bool canFoldMemoryOperand(const MachineInstr *MI,
113 const SmallVectorImpl<unsigned> &Ops) const override;
114 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
115 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
116 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
117 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
118 SmallVectorImpl<SDNode *> &NewNodes) const override;
119 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
120 bool UnfoldLoad, bool UnfoldStore,
121 unsigned *LoadRegIndex = nullptr) const override;
123 bool enableClusterLoads() const override;
125 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
126 int64_t Offset1, int64_t Offset2,
127 unsigned NumLoads) const override;
130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
131 void insertNoop(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator MI) const override;
133 bool isPredicated(const MachineInstr *MI) const override;
134 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
135 const SmallVectorImpl<MachineOperand> &Pred2) const override;
136 bool DefinesPredicate(MachineInstr *MI,
137 std::vector<MachineOperand> &Pred) const override;
138 bool isPredicable(MachineInstr *MI) const override;
139 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
141 // Helper functions that check the opcode for status information
142 bool isRegisterStore(const MachineInstr &MI) const;
143 bool isRegisterLoad(const MachineInstr &MI) const;
145 //===---------------------------------------------------------------------===//
146 // Pure virtual funtions to be implemented by sub-classes.
147 //===---------------------------------------------------------------------===//
149 virtual bool isMov(unsigned opcode) const = 0;
151 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and
154 /// We model indirect addressing using a virtual address space that can be
155 /// accesed with loads and stores. The "Indirect Address" is the memory
156 /// address in this virtual address space that maps to the given \p RegIndex
158 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
159 unsigned Channel) const = 0;
161 /// \returns The register class to be used for loading and storing values
162 /// from an "Indirect Address" .
163 virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
165 /// \brief Build instruction(s) for an indirect register write.
167 /// \returns The instruction that performs the indirect register write
168 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
169 MachineBasicBlock::iterator I,
170 unsigned ValueReg, unsigned Address,
171 unsigned OffsetReg) const = 0;
173 /// \brief Build instruction(s) for an indirect register read.
175 /// \returns The instruction that performs the indirect register read
176 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
177 MachineBasicBlock::iterator I,
178 unsigned ValueReg, unsigned Address,
179 unsigned OffsetReg) const = 0;
181 /// \brief Build a MOV instruction.
182 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
183 MachineBasicBlock::iterator I,
184 unsigned DstReg, unsigned SrcReg) const = 0;
186 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
187 /// equivalent opcode that writes \p Channels Channels.
188 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
193 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
194 } // End namespace AMDGPU
196 } // End llvm namespace
198 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
199 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
201 #endif // AMDGPUINSTRINFO_H