1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
31 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
34 //===----------------------------------------------------------------------===//
38 // This argument to this node is a dword address.
39 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
41 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
42 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
45 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
48 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
50 // out = 1.0 / sqrt(a)
51 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
53 // out = 1.0 / sqrt(a)
54 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
56 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
57 def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>;
59 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
61 // out = max(a, b) a and b are floats
62 def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]
66 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
67 def AMDGPUmad : SDNode<"AMDGPUISD::MAD", SDTFPTernaryOp, []>;
69 // out = max(a, b) a and b are signed ints
70 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
71 [SDNPCommutative, SDNPAssociative]
74 // out = max(a, b) a and b are unsigned ints
75 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
76 [SDNPCommutative, SDNPAssociative]
79 // out = min(a, b) a and b are floats
80 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
81 [SDNPCommutative, SDNPAssociative]
84 // out = min(a, b) a snd b are signed ints
85 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
86 [SDNPCommutative, SDNPAssociative]
89 // out = min(a, b) a and b are unsigned ints
90 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
91 [SDNPCommutative, SDNPAssociative]
95 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
97 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
99 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
101 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
105 // urecip - This operation is a helper for integer division, it returns the
106 // result of 1 / a as a fractional unsigned integer.
107 // out = (2^32 / a) + e
108 // e is rounding error
109 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
111 // Special case divide preop and flags.
112 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
114 // Special case divide FMA with scale and flags (src0 = Quotient,
115 // src1 = Denominator, src2 = Numerator).
116 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", SDTFPTernaryOp>;
118 // Single or double precision division fixup.
119 // Special case divide fixup and flags(src0 = Quotient, src1 =
120 // Denominator, src2 = Numerator).
121 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
123 // Look Up 2.0 / pi src0 with segment select src1[4:0]
124 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
126 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
127 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
128 [SDNPHasChain, SDNPMayLoad]>;
130 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
131 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
132 [SDNPHasChain, SDNPMayStore]>;
134 // MSKOR instructions are atomic memory instructions used mainly for storing
135 // 8-bit and 16-bit values. The definition is:
137 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
139 // src0: vec4(src, 0, 0, mask)
140 // src1: dst - rat offset (aka pointer) in dwords
141 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
142 SDTypeProfile<0, 2, []>,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
145 def AMDGPUround : SDNode<"ISD::FROUND",
146 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
148 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
149 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
150 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
151 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
153 def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>;
155 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
156 // performing the mulitply. The result is a 32-bit value.
157 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
160 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
164 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
167 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
171 //===----------------------------------------------------------------------===//
172 // Flow Control Profile Types
173 //===----------------------------------------------------------------------===//
174 // Branch instruction where second and third are basic blocks
175 def SDTIL_BRCond : SDTypeProfile<0, 2, [
179 //===----------------------------------------------------------------------===//
180 // Flow Control DAG Nodes
181 //===----------------------------------------------------------------------===//
182 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
184 //===----------------------------------------------------------------------===//
185 // Call/Return DAG Nodes
186 //===----------------------------------------------------------------------===//
187 def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
188 [SDNPHasChain, SDNPOptInGlue]>;