1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
27 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
30 //===----------------------------------------------------------------------===//
34 // This argument to this node is a dword address.
35 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
37 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
38 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
41 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
44 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
46 // out = 1.0 / sqrt(a)
47 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
49 // out = 1.0 / sqrt(a)
50 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
52 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
53 def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>;
55 // out = max(a, b) a and b are floats
56 def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
57 [SDNPCommutative, SDNPAssociative]
60 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
62 // out = max(a, b) a and b are signed ints
63 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
64 [SDNPCommutative, SDNPAssociative]
67 // out = max(a, b) a and b are unsigned ints
68 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
69 [SDNPCommutative, SDNPAssociative]
72 // out = min(a, b) a and b are floats
73 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
74 [SDNPCommutative, SDNPAssociative]
77 // out = min(a, b) a snd b are signed ints
78 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
79 [SDNPCommutative, SDNPAssociative]
82 // out = min(a, b) a and b are unsigned ints
83 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
84 [SDNPCommutative, SDNPAssociative]
88 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
90 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
92 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
94 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
98 // urecip - This operation is a helper for integer division, it returns the
99 // result of 1 / a as a fractional unsigned integer.
100 // out = (2^32 / a) + e
101 // e is rounding error
102 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
104 // Special case divide preop and flags.
105 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
107 // Special case divide FMA with scale and flags (src0 = Quotient,
108 // src1 = Denominator, src2 = Numerator).
109 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", SDTFPTernaryOp>;
111 // Single or double precision division fixup.
112 // Special case divide fixup and flags(src0 = Quotient, src1 =
113 // Denominator, src2 = Numerator).
114 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
116 // Look Up 2.0 / pi src0 with segment select src1[4:0]
117 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
119 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
120 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
121 [SDNPHasChain, SDNPMayLoad]>;
123 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
124 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
125 [SDNPHasChain, SDNPMayStore]>;
127 // MSKOR instructions are atomic memory instructions used mainly for storing
128 // 8-bit and 16-bit values. The definition is:
130 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
132 // src0: vec4(src, 0, 0, mask)
133 // src1: dst - rat offset (aka pointer) in dwords
134 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
135 SDTypeProfile<0, 2, []>,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def AMDGPUround : SDNode<"ISD::FROUND",
139 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
141 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
142 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
143 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
144 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
146 def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>;
148 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
149 // performing the mulitply. The result is a 32-bit value.
150 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
153 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
157 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
160 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
164 //===----------------------------------------------------------------------===//
165 // Flow Control Profile Types
166 //===----------------------------------------------------------------------===//
167 // Branch instruction where second and third are basic blocks
168 def SDTIL_BRCond : SDTypeProfile<0, 2, [
172 //===----------------------------------------------------------------------===//
173 // Flow Control DAG Nodes
174 //===----------------------------------------------------------------------===//
175 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
177 //===----------------------------------------------------------------------===//
178 // Call/Return DAG Nodes
179 //===----------------------------------------------------------------------===//
180 def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
181 [SDNPHasChain, SDNPOptInGlue]>;