1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
34 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
35 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
38 // float, float, float, vcc
39 def AMDGPUFmasOp : SDTypeProfile<1, 4,
40 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
43 //===----------------------------------------------------------------------===//
47 // This argument to this node is a dword address.
48 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
50 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
51 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
54 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
57 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
59 // out = 1.0 / sqrt(a)
60 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
62 // out = 1.0 / sqrt(a)
63 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
65 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
66 def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>;
68 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
70 def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
72 // out = max(a, b) a and b are floats, where a nan comparison fails.
73 // This is not commutative because this gives the second operand:
74 // x < nan ? x : nan -> nan
75 // nan < x ? nan : x -> x
76 def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
80 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
82 // out = max(a, b) a and b are signed ints
83 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
84 [SDNPCommutative, SDNPAssociative]
87 // out = max(a, b) a and b are unsigned ints
88 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
89 [SDNPCommutative, SDNPAssociative]
92 // out = min(a, b) a and b are floats, where a nan comparison fails.
93 def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
97 // out = min(a, b) a and b are signed ints
98 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
99 [SDNPCommutative, SDNPAssociative]
102 // out = min(a, b) a and b are unsigned ints
103 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
104 [SDNPCommutative, SDNPAssociative]
107 // FIXME: TableGen doesn't like commutative instructions with more
109 // out = max(a, b, c) a, b and c are floats
110 def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
111 [/*SDNPCommutative, SDNPAssociative*/]
114 // out = max(a, b, c) a, b, and c are signed ints
115 def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
116 [/*SDNPCommutative, SDNPAssociative*/]
119 // out = max(a, b, c) a, b and c are unsigned ints
120 def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
121 [/*SDNPCommutative, SDNPAssociative*/]
124 // out = min(a, b, c) a, b and c are floats
125 def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
126 [/*SDNPCommutative, SDNPAssociative*/]
129 // out = min(a, b, c) a, b and c are signed ints
130 def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
131 [/*SDNPCommutative, SDNPAssociative*/]
134 // out = min(a, b) a and b are unsigned ints
135 def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
136 [/*SDNPCommutative, SDNPAssociative*/]
139 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
141 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
143 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
145 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
149 // urecip - This operation is a helper for integer division, it returns the
150 // result of 1 / a as a fractional unsigned integer.
151 // out = (2^32 / a) + e
152 // e is rounding error
153 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
155 // Special case divide preop and flags.
156 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
158 // Special case divide FMA with scale and flags (src0 = Quotient,
159 // src1 = Denominator, src2 = Numerator).
160 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
162 // Single or double precision division fixup.
163 // Special case divide fixup and flags(src0 = Quotient, src1 =
164 // Denominator, src2 = Numerator).
165 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
167 // Look Up 2.0 / pi src0 with segment select src1[4:0]
168 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
170 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
171 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
172 [SDNPHasChain, SDNPMayLoad]>;
174 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
175 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
176 [SDNPHasChain, SDNPMayStore]>;
178 // MSKOR instructions are atomic memory instructions used mainly for storing
179 // 8-bit and 16-bit values. The definition is:
181 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
183 // src0: vec4(src, 0, 0, mask)
184 // src1: dst - rat offset (aka pointer) in dwords
185 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
186 SDTypeProfile<0, 2, []>,
187 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
189 def AMDGPUround : SDNode<"ISD::FROUND",
190 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
192 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
193 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
194 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
195 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
197 def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>;
199 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
200 // performing the mulitply. The result is a 32-bit value.
201 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
204 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
208 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
211 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
215 //===----------------------------------------------------------------------===//
216 // Flow Control Profile Types
217 //===----------------------------------------------------------------------===//
218 // Branch instruction where second and third are basic blocks
219 def SDTIL_BRCond : SDTypeProfile<0, 2, [
223 //===----------------------------------------------------------------------===//
224 // Flow Control DAG Nodes
225 //===----------------------------------------------------------------------===//
226 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
228 //===----------------------------------------------------------------------===//
229 // Call/Return DAG Nodes
230 //===----------------------------------------------------------------------===//
231 def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
232 [SDNPHasChain, SDNPOptInGlue]>;