1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 //===----------------------------------------------------------------------===//
26 // out = ((a << 32) | b) >> c)
28 // Can be used to optimize rtol:
29 // rotl(a, b) = bitalign(a, a, 32 - b)
30 def AMDGPUbitalign : SDNode<"AMDGPUISD::BITALIGN", AMDGPUDTIntTernaryOp>;
32 // This argument to this node is a dword address.
33 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
36 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
38 // out = max(a, b) a and b are floats
39 def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
40 [SDNPCommutative, SDNPAssociative]
43 // out = max(a, b) a and b are signed ints
44 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
45 [SDNPCommutative, SDNPAssociative]
48 // out = max(a, b) a and b are unsigned ints
49 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
50 [SDNPCommutative, SDNPAssociative]
53 // out = min(a, b) a and b are floats
54 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
55 [SDNPCommutative, SDNPAssociative]
58 // out = min(a, b) a snd b are signed ints
59 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
60 [SDNPCommutative, SDNPAssociative]
63 // out = min(a, b) a and b are unsigned ints
64 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
65 [SDNPCommutative, SDNPAssociative]
68 // urecip - This operation is a helper for integer division, it returns the
69 // result of 1 / a as a fractional unsigned integer.
70 // out = (2^32 / a) + e
71 // e is rounding error
72 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
74 def fpow : SDNode<"ISD::FPOW", SDTFPBinOp>;
76 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
77 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
78 [SDNPHasChain, SDNPMayLoad]>;
80 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
81 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
82 [SDNPHasChain, SDNPMayStore]>;