1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
34 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
35 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
38 // float, float, float, vcc
39 def AMDGPUFmasOp : SDTypeProfile<1, 4,
40 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
43 //===----------------------------------------------------------------------===//
47 // This argument to this node is a dword address.
48 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
50 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
51 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
54 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
57 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
59 // out = 1.0 / sqrt(a)
60 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
62 // out = 1.0 / sqrt(a)
63 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
65 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
66 def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>;
68 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
70 def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
72 // out = max(a, b) a and b are floats, where a nan comparison fails.
73 // This is not commutative because this gives the second operand:
74 // x < nan ? x : nan -> nan
75 // nan < x ? nan : x -> x
76 def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
80 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
81 def AMDGPUmad : SDNode<"AMDGPUISD::MAD", SDTFPTernaryOp, []>;
83 // out = max(a, b) a and b are signed ints
84 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
85 [SDNPCommutative, SDNPAssociative]
88 // out = max(a, b) a and b are unsigned ints
89 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
90 [SDNPCommutative, SDNPAssociative]
93 // out = min(a, b) a and b are floats, where a nan comparison fails.
94 def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
98 // out = min(a, b) a and b are signed ints
99 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
100 [SDNPCommutative, SDNPAssociative]
103 // out = min(a, b) a and b are unsigned ints
104 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
105 [SDNPCommutative, SDNPAssociative]
108 // FIXME: TableGen doesn't like commutative instructions with more
110 // out = max(a, b, c) a, b and c are floats
111 def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
112 [/*SDNPCommutative, SDNPAssociative*/]
115 // out = max(a, b, c) a, b, and c are signed ints
116 def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
117 [/*SDNPCommutative, SDNPAssociative*/]
120 // out = max(a, b, c) a, b and c are unsigned ints
121 def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
122 [/*SDNPCommutative, SDNPAssociative*/]
125 // out = min(a, b, c) a, b and c are floats
126 def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
127 [/*SDNPCommutative, SDNPAssociative*/]
130 // out = min(a, b, c) a, b and c are signed ints
131 def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
132 [/*SDNPCommutative, SDNPAssociative*/]
135 // out = min(a, b) a and b are unsigned ints
136 def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
137 [/*SDNPCommutative, SDNPAssociative*/]
140 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
142 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
144 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
146 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
150 // urecip - This operation is a helper for integer division, it returns the
151 // result of 1 / a as a fractional unsigned integer.
152 // out = (2^32 / a) + e
153 // e is rounding error
154 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
156 // Special case divide preop and flags.
157 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
159 // Special case divide FMA with scale and flags (src0 = Quotient,
160 // src1 = Denominator, src2 = Numerator).
161 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
163 // Single or double precision division fixup.
164 // Special case divide fixup and flags(src0 = Quotient, src1 =
165 // Denominator, src2 = Numerator).
166 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
168 // Look Up 2.0 / pi src0 with segment select src1[4:0]
169 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
171 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
172 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
173 [SDNPHasChain, SDNPMayLoad]>;
175 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
176 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
177 [SDNPHasChain, SDNPMayStore]>;
179 // MSKOR instructions are atomic memory instructions used mainly for storing
180 // 8-bit and 16-bit values. The definition is:
182 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
184 // src0: vec4(src, 0, 0, mask)
185 // src1: dst - rat offset (aka pointer) in dwords
186 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
187 SDTypeProfile<0, 2, []>,
188 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
190 def AMDGPUround : SDNode<"ISD::FROUND",
191 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
193 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
194 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
195 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
196 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
198 def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>;
200 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
201 // performing the mulitply. The result is a 32-bit value.
202 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
205 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
209 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
212 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
216 //===----------------------------------------------------------------------===//
217 // Flow Control Profile Types
218 //===----------------------------------------------------------------------===//
219 // Branch instruction where second and third are basic blocks
220 def SDTIL_BRCond : SDTypeProfile<0, 2, [
224 //===----------------------------------------------------------------------===//
225 // Flow Control DAG Nodes
226 //===----------------------------------------------------------------------===//
227 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
229 //===----------------------------------------------------------------------===//
230 // Call/Return DAG Nodes
231 //===----------------------------------------------------------------------===//
232 def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
233 [SDNPHasChain, SDNPOptInGlue]>;