1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_OEQ : PatLeaf <
48 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
51 def COND_NE : PatLeaf <
53 [{switch(N->get()){{default: return false;
54 case ISD::SETONE: case ISD::SETUNE:
55 case ISD::SETNE: return true;}}}]
58 def COND_UNE : PatLeaf <
60 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
63 def COND_GT : PatLeaf <
65 [{switch(N->get()){{default: return false;
66 case ISD::SETOGT: case ISD::SETUGT:
67 case ISD::SETGT: return true;}}}]
70 def COND_OGT : PatLeaf <
72 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
75 def COND_GE : PatLeaf <
77 [{switch(N->get()){{default: return false;
78 case ISD::SETOGE: case ISD::SETUGE:
79 case ISD::SETGE: return true;}}}]
82 def COND_OGE : PatLeaf <
84 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
87 def COND_LT : PatLeaf <
89 [{switch(N->get()){{default: return false;
90 case ISD::SETOLT: case ISD::SETULT:
91 case ISD::SETLT: return true;}}}]
94 def COND_LE : PatLeaf <
96 [{switch(N->get()){{default: return false;
97 case ISD::SETOLE: case ISD::SETULE:
98 case ISD::SETLE: return true;}}}]
101 def COND_NULL : PatLeaf <
106 //===----------------------------------------------------------------------===//
107 // Load/Store Pattern Fragments
108 //===----------------------------------------------------------------------===//
110 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
111 LoadSDNode *L = cast<LoadSDNode>(N);
112 return L->getExtensionType() == ISD::ZEXTLOAD ||
113 L->getExtensionType() == ISD::EXTLOAD;
116 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
117 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
120 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
121 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
124 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
125 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
128 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
129 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
132 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
133 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
136 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
137 return isLocalLoad(dyn_cast<LoadSDNode>(N));
140 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
141 return isLocalLoad(dyn_cast<LoadSDNode>(N));
144 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
145 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
148 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
149 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
152 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
153 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
156 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
157 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
160 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
161 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
164 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
165 return isLocalLoad(dyn_cast<LoadSDNode>(N));
168 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
169 return isLocalLoad(dyn_cast<LoadSDNode>(N));
172 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
173 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
176 def az_extloadi32_global : PatFrag<(ops node:$ptr),
177 (az_extloadi32 node:$ptr), [{
178 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
181 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
182 (az_extloadi32 node:$ptr), [{
183 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
186 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
187 (truncstorei8 node:$val, node:$ptr), [{
188 return isGlobalStore(dyn_cast<StoreSDNode>(N));
191 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
192 (truncstorei16 node:$val, node:$ptr), [{
193 return isGlobalStore(dyn_cast<StoreSDNode>(N));
196 def local_store : PatFrag<(ops node:$val, node:$ptr),
197 (store node:$val, node:$ptr), [{
198 return isLocalStore(dyn_cast<StoreSDNode>(N));
201 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
202 (truncstorei8 node:$val, node:$ptr), [{
203 return isLocalStore(dyn_cast<StoreSDNode>(N));
206 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
207 (truncstorei16 node:$val, node:$ptr), [{
208 return isLocalStore(dyn_cast<StoreSDNode>(N));
211 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
212 return isLocalLoad(dyn_cast<LoadSDNode>(N));
215 def atomic_load_add_local : PatFrag<(ops node:$ptr, node:$value),
216 (atomic_load_add node:$ptr, node:$value), [{
217 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
220 def atomic_load_sub_local : PatFrag<(ops node:$ptr, node:$value),
221 (atomic_load_sub node:$ptr, node:$value), [{
222 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
225 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
226 (AMDGPUstore_mskor node:$val, node:$ptr), [{
227 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
231 int TWO_PI = 0x40c90fdb;
233 int TWO_PI_INV = 0x3e22f983;
234 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
236 def CONST : Constants;
238 def FP_ZERO : PatLeaf <
240 [{return N->getValueAPF().isZero();}]
243 def FP_ONE : PatLeaf <
245 [{return N->isExactlyValue(1.0);}]
248 def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
249 def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
251 let isCodeGenOnly = 1, isPseudo = 1 in {
253 let usesCustomInserter = 1 in {
255 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
259 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
262 class FABS <RegisterClass rc> : AMDGPUShaderInst <
266 [(set f32:$dst, (fabs f32:$src0))]
269 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
273 [(set f32:$dst, (fneg f32:$src0))]
276 } // usesCustomInserter = 1
278 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
279 ComplexPattern addrPat> {
280 def RegisterLoad : AMDGPUShaderInst <
281 (outs dstClass:$dst),
282 (ins addrClass:$addr, i32imm:$chan),
283 "RegisterLoad $dst, $addr",
284 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
286 let isRegisterLoad = 1;
289 def RegisterStore : AMDGPUShaderInst <
291 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
292 "RegisterStore $val, $addr",
293 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
295 let isRegisterStore = 1;
299 } // End isCodeGenOnly = 1, isPseudo = 1
301 /* Generic helper patterns for intrinsics */
302 /* -------------------------------------- */
304 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
306 (fpow f32:$src0, f32:$src1),
307 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
310 /* Other helper patterns */
311 /* --------------------- */
313 /* Extract element pattern */
314 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
317 (sub_type (vector_extract vec_type:$src, sub_idx)),
318 (EXTRACT_SUBREG $src, sub_reg)
321 /* Insert element pattern */
322 class Insert_Element <ValueType elem_type, ValueType vec_type,
323 int sub_idx, SubRegIndex sub_reg>
325 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
326 (INSERT_SUBREG $vec, $elem, sub_reg)
329 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
330 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
331 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
332 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
335 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
336 // can handle COPY instructions.
337 // bitconvert pattern
338 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
339 (dt (bitconvert (st rc:$src0))),
343 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
344 // can handle COPY instructions.
345 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
346 (vt (AMDGPUdwordaddr (vt rc:$addr))),
352 multiclass BFIPatterns <Instruction BFI_INT> {
354 // Definition from ISA doc:
355 // (y & x) | (z & ~x)
357 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
361 // SHA-256 Ch function
364 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
370 // SHA-256 Ma patterns
372 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
373 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
374 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
375 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
378 // Bitfield extract patterns
380 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
381 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
382 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
384 class BFEPattern <Instruction BFE> : Pat <
385 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
390 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
391 (rotr i32:$src0, i32:$src1),
392 (BIT_ALIGN $src0, $src0, $src1)
395 // 24-bit arithmetic patterns
396 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
399 class UMUL24Pattern <Instruction UMUL24> : Pat <
400 (mul U24:$x, U24:$y),
405 include "R600Instructions.td"
407 include "SIInstrInfo.td"