1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
38 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
40 //===----------------------------------------------------------------------===//
41 // PatLeafs for floating-point comparisons
42 //===----------------------------------------------------------------------===//
44 def COND_OEQ : PatLeaf <
46 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
49 def COND_OGT : PatLeaf <
51 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
54 def COND_OGE : PatLeaf <
56 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
59 def COND_OLT : PatLeaf <
61 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
64 def COND_OLE : PatLeaf <
66 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
69 def COND_UNE : PatLeaf <
71 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
74 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
75 def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
77 //===----------------------------------------------------------------------===//
78 // PatLeafs for unsigned comparisons
79 //===----------------------------------------------------------------------===//
81 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
82 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
83 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
84 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
86 //===----------------------------------------------------------------------===//
87 // PatLeafs for signed comparisons
88 //===----------------------------------------------------------------------===//
90 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
91 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
92 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
93 def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
95 //===----------------------------------------------------------------------===//
96 // PatLeafs for integer equality
97 //===----------------------------------------------------------------------===//
99 def COND_EQ : PatLeaf <
101 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
104 def COND_NE : PatLeaf <
106 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
109 def COND_NULL : PatLeaf <
114 //===----------------------------------------------------------------------===//
115 // Load/Store Pattern Fragments
116 //===----------------------------------------------------------------------===//
118 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
119 LoadSDNode *L = cast<LoadSDNode>(N);
120 return L->getExtensionType() == ISD::ZEXTLOAD ||
121 L->getExtensionType() == ISD::EXTLOAD;
124 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
125 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
128 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
129 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
132 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
133 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
136 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
137 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
140 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
141 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
144 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
145 return isLocalLoad(dyn_cast<LoadSDNode>(N));
148 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
149 return isLocalLoad(dyn_cast<LoadSDNode>(N));
152 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
153 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
156 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
157 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
160 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
161 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
164 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
165 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
168 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
169 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
172 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
173 return isLocalLoad(dyn_cast<LoadSDNode>(N));
176 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
177 return isLocalLoad(dyn_cast<LoadSDNode>(N));
180 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
181 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
184 def az_extloadi32_global : PatFrag<(ops node:$ptr),
185 (az_extloadi32 node:$ptr), [{
186 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
189 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
190 (az_extloadi32 node:$ptr), [{
191 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
194 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
195 (truncstorei8 node:$val, node:$ptr), [{
196 return isGlobalStore(dyn_cast<StoreSDNode>(N));
199 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
200 (truncstorei16 node:$val, node:$ptr), [{
201 return isGlobalStore(dyn_cast<StoreSDNode>(N));
204 def local_store : PatFrag<(ops node:$val, node:$ptr),
205 (store node:$val, node:$ptr), [{
206 return isLocalStore(dyn_cast<StoreSDNode>(N));
209 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
210 (truncstorei8 node:$val, node:$ptr), [{
211 return isLocalStore(dyn_cast<StoreSDNode>(N));
214 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
215 (truncstorei16 node:$val, node:$ptr), [{
216 return isLocalStore(dyn_cast<StoreSDNode>(N));
219 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
220 return isLocalLoad(dyn_cast<LoadSDNode>(N));
223 def atomic_load_add_local : PatFrag<(ops node:$ptr, node:$value),
224 (atomic_load_add node:$ptr, node:$value), [{
225 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
228 def atomic_load_sub_local : PatFrag<(ops node:$ptr, node:$value),
229 (atomic_load_sub node:$ptr, node:$value), [{
230 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
233 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
234 (AMDGPUstore_mskor node:$val, node:$ptr), [{
235 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
239 int TWO_PI = 0x40c90fdb;
241 int TWO_PI_INV = 0x3e22f983;
242 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
244 def CONST : Constants;
246 def FP_ZERO : PatLeaf <
248 [{return N->getValueAPF().isZero();}]
251 def FP_ONE : PatLeaf <
253 [{return N->isExactlyValue(1.0);}]
256 def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
257 def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
259 let isCodeGenOnly = 1, isPseudo = 1 in {
261 let usesCustomInserter = 1 in {
263 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
267 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
270 class FABS <RegisterClass rc> : AMDGPUShaderInst <
274 [(set f32:$dst, (fabs f32:$src0))]
277 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
281 [(set f32:$dst, (fneg f32:$src0))]
284 } // usesCustomInserter = 1
286 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
287 ComplexPattern addrPat> {
288 let UseNamedOperandTable = 1 in {
290 def RegisterLoad : AMDGPUShaderInst <
291 (outs dstClass:$dst),
292 (ins addrClass:$addr, i32imm:$chan),
293 "RegisterLoad $dst, $addr",
294 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
296 let isRegisterLoad = 1;
299 def RegisterStore : AMDGPUShaderInst <
301 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
302 "RegisterStore $val, $addr",
303 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
305 let isRegisterStore = 1;
310 } // End isCodeGenOnly = 1, isPseudo = 1
312 /* Generic helper patterns for intrinsics */
313 /* -------------------------------------- */
315 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
317 (fpow f32:$src0, f32:$src1),
318 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
321 /* Other helper patterns */
322 /* --------------------- */
324 /* Extract element pattern */
325 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
328 (sub_type (vector_extract vec_type:$src, sub_idx)),
329 (EXTRACT_SUBREG $src, sub_reg)
332 /* Insert element pattern */
333 class Insert_Element <ValueType elem_type, ValueType vec_type,
334 int sub_idx, SubRegIndex sub_reg>
336 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
337 (INSERT_SUBREG $vec, $elem, sub_reg)
340 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
341 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
342 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
343 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
346 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
347 // can handle COPY instructions.
348 // bitconvert pattern
349 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
350 (dt (bitconvert (st rc:$src0))),
354 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
355 // can handle COPY instructions.
356 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
357 (vt (AMDGPUdwordaddr (vt rc:$addr))),
363 multiclass BFIPatterns <Instruction BFI_INT> {
365 // Definition from ISA doc:
366 // (y & x) | (z & ~x)
368 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
372 // SHA-256 Ch function
375 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
381 // SHA-256 Ma patterns
383 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
384 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
385 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
386 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
389 // Bitfield extract patterns
391 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
392 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
393 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
395 class BFEPattern <Instruction BFE> : Pat <
396 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
401 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
402 (rotr i32:$src0, i32:$src1),
403 (BIT_ALIGN $src0, $src0, $src1)
406 // 24-bit arithmetic patterns
407 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
410 class UMUL24Pattern <Instruction UMUL24> : Pat <
411 (mul U24:$x, U24:$y),
416 include "R600Instructions.td"
418 include "SIInstrInfo.td"