1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_NE : PatLeaf <
48 [{switch(N->get()){{default: return false;
49 case ISD::SETONE: case ISD::SETUNE:
50 case ISD::SETNE: return true;}}}]
52 def COND_GT : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETOGT: case ISD::SETUGT:
56 case ISD::SETGT: return true;}}}]
59 def COND_GE : PatLeaf <
61 [{switch(N->get()){{default: return false;
62 case ISD::SETOGE: case ISD::SETUGE:
63 case ISD::SETGE: return true;}}}]
66 def COND_LT : PatLeaf <
68 [{switch(N->get()){{default: return false;
69 case ISD::SETOLT: case ISD::SETULT:
70 case ISD::SETLT: return true;}}}]
73 def COND_LE : PatLeaf <
75 [{switch(N->get()){{default: return false;
76 case ISD::SETOLE: case ISD::SETULE:
77 case ISD::SETLE: return true;}}}]
80 def COND_NULL : PatLeaf <
85 //===----------------------------------------------------------------------===//
86 // Load/Store Pattern Fragments
87 //===----------------------------------------------------------------------===//
89 def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
90 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
94 int TWO_PI = 0x40c90fdb;
96 int TWO_PI_INV = 0x3e22f983;
97 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
99 def CONST : Constants;
101 def FP_ZERO : PatLeaf <
103 [{return N->getValueAPF().isZero();}]
106 def FP_ONE : PatLeaf <
108 [{return N->isExactlyValue(1.0);}]
111 let isCodeGenOnly = 1, isPseudo = 1 in {
113 let usesCustomInserter = 1 in {
115 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
119 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
122 class FABS <RegisterClass rc> : AMDGPUShaderInst <
126 [(set f32:$dst, (fabs f32:$src0))]
129 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
133 [(set f32:$dst, (fneg f32:$src0))]
136 } // usesCustomInserter = 1
138 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
139 ComplexPattern addrPat> {
140 def RegisterLoad : AMDGPUShaderInst <
141 (outs dstClass:$dst),
142 (ins addrClass:$addr, i32imm:$chan),
143 "RegisterLoad $dst, $addr",
144 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
146 let isRegisterLoad = 1;
149 def RegisterStore : AMDGPUShaderInst <
151 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
152 "RegisterStore $val, $addr",
153 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
155 let isRegisterStore = 1;
159 } // End isCodeGenOnly = 1, isPseudo = 1
161 /* Generic helper patterns for intrinsics */
162 /* -------------------------------------- */
164 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
166 (fpow f32:$src0, f32:$src1),
167 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
170 /* Other helper patterns */
171 /* --------------------- */
173 /* Extract element pattern */
174 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
177 (sub_type (vector_extract vec_type:$src, sub_idx)),
178 (EXTRACT_SUBREG $src, sub_reg)
181 /* Insert element pattern */
182 class Insert_Element <ValueType elem_type, ValueType vec_type,
183 int sub_idx, SubRegIndex sub_reg>
185 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
186 (INSERT_SUBREG $vec, $elem, sub_reg)
189 // Vector Build pattern
190 class Vector1_Build <ValueType vecType, ValueType elemType,
191 RegisterClass rc> : Pat <
192 (vecType (build_vector elemType:$src)),
193 (vecType (COPY_TO_REGCLASS $src, rc))
196 class Vector2_Build <ValueType vecType, ValueType elemType> : Pat <
197 (vecType (build_vector elemType:$sub0, elemType:$sub1)),
198 (INSERT_SUBREG (INSERT_SUBREG
199 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1)
202 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
203 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
204 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
205 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
208 class Vector8_Build <ValueType vecType, ValueType elemType> : Pat <
209 (vecType (build_vector elemType:$sub0, elemType:$sub1,
210 elemType:$sub2, elemType:$sub3,
211 elemType:$sub4, elemType:$sub5,
212 elemType:$sub6, elemType:$sub7)),
213 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
214 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
215 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1),
216 $sub2, sub2), $sub3, sub3),
217 $sub4, sub4), $sub5, sub5),
218 $sub6, sub6), $sub7, sub7)
221 class Vector16_Build <ValueType vecType, ValueType elemType> : Pat <
222 (vecType (build_vector elemType:$sub0, elemType:$sub1,
223 elemType:$sub2, elemType:$sub3,
224 elemType:$sub4, elemType:$sub5,
225 elemType:$sub6, elemType:$sub7,
226 elemType:$sub8, elemType:$sub9,
227 elemType:$sub10, elemType:$sub11,
228 elemType:$sub12, elemType:$sub13,
229 elemType:$sub14, elemType:$sub15)),
230 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
231 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
232 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
233 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
234 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1),
235 $sub2, sub2), $sub3, sub3),
236 $sub4, sub4), $sub5, sub5),
237 $sub6, sub6), $sub7, sub7),
238 $sub8, sub8), $sub9, sub9),
239 $sub10, sub10), $sub11, sub11),
240 $sub12, sub12), $sub13, sub13),
241 $sub14, sub14), $sub15, sub15)
244 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
245 // can handle COPY instructions.
246 // bitconvert pattern
247 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
248 (dt (bitconvert (st rc:$src0))),
252 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
253 // can handle COPY instructions.
254 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
255 (vt (AMDGPUdwordaddr (vt rc:$addr))),
261 multiclass BFIPatterns <Instruction BFI_INT> {
263 // Definition from ISA doc:
264 // (y & x) | (z & ~x)
266 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
270 // SHA-256 Ch function
273 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
279 // SHA-256 Ma patterns
281 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
282 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
283 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
284 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
287 // Bitfield extract patterns
289 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
290 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
291 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
293 class BFEPattern <Instruction BFE> : Pat <
294 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
298 include "R600Instructions.td"
300 include "SIInstrInfo.td"