1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_NE : PatLeaf <
48 [{switch(N->get()){{default: return false;
49 case ISD::SETONE: case ISD::SETUNE:
50 case ISD::SETNE: return true;}}}]
52 def COND_GT : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETOGT: case ISD::SETUGT:
56 case ISD::SETGT: return true;}}}]
59 def COND_GE : PatLeaf <
61 [{switch(N->get()){{default: return false;
62 case ISD::SETOGE: case ISD::SETUGE:
63 case ISD::SETGE: return true;}}}]
66 def COND_LT : PatLeaf <
68 [{switch(N->get()){{default: return false;
69 case ISD::SETOLT: case ISD::SETULT:
70 case ISD::SETLT: return true;}}}]
73 def COND_LE : PatLeaf <
75 [{switch(N->get()){{default: return false;
76 case ISD::SETOLE: case ISD::SETULE:
77 case ISD::SETLE: return true;}}}]
80 def COND_NULL : PatLeaf <
85 //===----------------------------------------------------------------------===//
86 // Load/Store Pattern Fragments
87 //===----------------------------------------------------------------------===//
89 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
90 LoadSDNode *L = cast<LoadSDNode>(N);
91 return L->getExtensionType() == ISD::ZEXTLOAD ||
92 L->getExtensionType() == ISD::EXTLOAD;
95 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
96 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
99 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
100 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
103 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
104 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
107 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
108 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
111 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
112 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
115 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
116 return isLocalLoad(dyn_cast<LoadSDNode>(N));
119 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
120 return isLocalLoad(dyn_cast<LoadSDNode>(N));
123 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
124 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
127 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
128 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
131 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
132 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
135 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
136 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
139 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
140 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
143 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
144 return isLocalLoad(dyn_cast<LoadSDNode>(N));
147 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
148 return isLocalLoad(dyn_cast<LoadSDNode>(N));
151 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
152 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
155 def az_extloadi32_global : PatFrag<(ops node:$ptr),
156 (az_extloadi32 node:$ptr), [{
157 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
160 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
161 (az_extloadi32 node:$ptr), [{
162 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
165 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
166 (truncstorei8 node:$val, node:$ptr), [{
167 return isGlobalStore(dyn_cast<StoreSDNode>(N));
170 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
171 (truncstorei16 node:$val, node:$ptr), [{
172 return isGlobalStore(dyn_cast<StoreSDNode>(N));
175 def local_store : PatFrag<(ops node:$val, node:$ptr),
176 (store node:$val, node:$ptr), [{
177 return isLocalStore(dyn_cast<StoreSDNode>(N));
180 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
181 (truncstorei8 node:$val, node:$ptr), [{
182 return isLocalStore(dyn_cast<StoreSDNode>(N));
185 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
186 (truncstorei16 node:$val, node:$ptr), [{
187 return isLocalStore(dyn_cast<StoreSDNode>(N));
190 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
191 return isLocalLoad(dyn_cast<LoadSDNode>(N));
194 def atomic_load_add_local : PatFrag<(ops node:$ptr, node:$value),
195 (atomic_load_add node:$ptr, node:$value), [{
196 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
199 def atomic_load_sub_local : PatFrag<(ops node:$ptr, node:$value),
200 (atomic_load_sub node:$ptr, node:$value), [{
201 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
204 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
205 (AMDGPUstore_mskor node:$val, node:$ptr), [{
206 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
210 int TWO_PI = 0x40c90fdb;
212 int TWO_PI_INV = 0x3e22f983;
213 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
215 def CONST : Constants;
217 def FP_ZERO : PatLeaf <
219 [{return N->getValueAPF().isZero();}]
222 def FP_ONE : PatLeaf <
224 [{return N->isExactlyValue(1.0);}]
227 def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
228 def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
230 let isCodeGenOnly = 1, isPseudo = 1 in {
232 let usesCustomInserter = 1 in {
234 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
238 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
241 class FABS <RegisterClass rc> : AMDGPUShaderInst <
245 [(set f32:$dst, (fabs f32:$src0))]
248 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
252 [(set f32:$dst, (fneg f32:$src0))]
255 } // usesCustomInserter = 1
257 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
258 ComplexPattern addrPat> {
259 def RegisterLoad : AMDGPUShaderInst <
260 (outs dstClass:$dst),
261 (ins addrClass:$addr, i32imm:$chan),
262 "RegisterLoad $dst, $addr",
263 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
265 let isRegisterLoad = 1;
268 def RegisterStore : AMDGPUShaderInst <
270 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
271 "RegisterStore $val, $addr",
272 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
274 let isRegisterStore = 1;
278 } // End isCodeGenOnly = 1, isPseudo = 1
280 /* Generic helper patterns for intrinsics */
281 /* -------------------------------------- */
283 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
285 (fpow f32:$src0, f32:$src1),
286 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
289 /* Other helper patterns */
290 /* --------------------- */
292 /* Extract element pattern */
293 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
296 (sub_type (vector_extract vec_type:$src, sub_idx)),
297 (EXTRACT_SUBREG $src, sub_reg)
300 /* Insert element pattern */
301 class Insert_Element <ValueType elem_type, ValueType vec_type,
302 int sub_idx, SubRegIndex sub_reg>
304 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
305 (INSERT_SUBREG $vec, $elem, sub_reg)
308 class Vector4_Build <ValueType vecType, ValueType elemType> : Pat <
309 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)),
310 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
311 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
314 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
315 // can handle COPY instructions.
316 // bitconvert pattern
317 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
318 (dt (bitconvert (st rc:$src0))),
322 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
323 // can handle COPY instructions.
324 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
325 (vt (AMDGPUdwordaddr (vt rc:$addr))),
331 multiclass BFIPatterns <Instruction BFI_INT> {
333 // Definition from ISA doc:
334 // (y & x) | (z & ~x)
336 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
340 // SHA-256 Ch function
343 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
349 // SHA-256 Ma patterns
351 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
352 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
353 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
354 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
357 // Bitfield extract patterns
359 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
360 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
361 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
363 class BFEPattern <Instruction BFE> : Pat <
364 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
369 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
370 (rotr i32:$src0, i32:$src1),
371 (BIT_ALIGN $src0, $src0, $src1)
374 // 24-bit arithmetic patterns
375 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
378 class UMUL24Pattern <Instruction UMUL24> : Pat <
379 (mul U24:$x, U24:$y),
384 include "R600Instructions.td"
386 include "SIInstrInfo.td"