1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bits<16> AMDILOp = 0;
17 field bits<3> Gen = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
25 let TSFlags{42-40} = Gen;
26 let TSFlags{63-48} = AMDILOp;
29 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
30 : AMDGPUInst<outs, ins, asm, pattern> {
32 field bits<32> Inst = 0xffffffff;
36 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
38 def COND_EQ : PatLeaf <
40 [{switch(N->get()){{default: return false;
41 case ISD::SETOEQ: case ISD::SETUEQ:
42 case ISD::SETEQ: return true;}}}]
45 def COND_NE : PatLeaf <
47 [{switch(N->get()){{default: return false;
48 case ISD::SETONE: case ISD::SETUNE:
49 case ISD::SETNE: return true;}}}]
51 def COND_GT : PatLeaf <
53 [{switch(N->get()){{default: return false;
54 case ISD::SETOGT: case ISD::SETUGT:
55 case ISD::SETGT: return true;}}}]
58 def COND_GE : PatLeaf <
60 [{switch(N->get()){{default: return false;
61 case ISD::SETOGE: case ISD::SETUGE:
62 case ISD::SETGE: return true;}}}]
65 def COND_LT : PatLeaf <
67 [{switch(N->get()){{default: return false;
68 case ISD::SETOLT: case ISD::SETULT:
69 case ISD::SETLT: return true;}}}]
72 def COND_LE : PatLeaf <
74 [{switch(N->get()){{default: return false;
75 case ISD::SETOLE: case ISD::SETULE:
76 case ISD::SETLE: return true;}}}]
79 //===----------------------------------------------------------------------===//
80 // Load/Store Pattern Fragments
81 //===----------------------------------------------------------------------===//
83 def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
84 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
88 int TWO_PI = 0x40c90fdb;
90 int TWO_PI_INV = 0x3e22f983;
92 def CONST : Constants;
94 def FP_ZERO : PatLeaf <
96 [{return N->getValueAPF().isZero();}]
99 def FP_ONE : PatLeaf <
101 [{return N->isExactlyValue(1.0);}]
104 let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in {
106 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
110 [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
113 class FABS <RegisterClass rc> : AMDGPUShaderInst <
117 [(set rc:$dst, (fabs rc:$src0))]
120 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
124 [(set rc:$dst, (fneg rc:$src0))]
127 def SHADER_TYPE : AMDGPUShaderInst <
131 [(int_AMDGPU_shader_type imm:$type)]
134 } // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1
136 /* Generic helper patterns for intrinsics */
137 /* -------------------------------------- */
139 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
140 RegisterClass rc> : Pat <
141 (fpow rc:$src0, rc:$src1),
142 (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
145 /* Other helper patterns */
146 /* --------------------- */
148 /* Extract element pattern */
149 class Extract_Element <ValueType sub_type, ValueType vec_type,
150 RegisterClass vec_class, int sub_idx,
151 SubRegIndex sub_reg>: Pat<
152 (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
153 (EXTRACT_SUBREG vec_class:$src, sub_reg)
156 /* Insert element pattern */
157 class Insert_Element <ValueType elem_type, ValueType vec_type,
158 RegisterClass elem_class, RegisterClass vec_class,
159 int sub_idx, SubRegIndex sub_reg> : Pat <
161 (vec_type (vector_insert (vec_type vec_class:$vec),
162 (elem_type elem_class:$elem), sub_idx)),
163 (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
166 // Vector Build pattern
167 class Vector_Build <ValueType vecType, RegisterClass vectorClass,
168 ValueType elemType, RegisterClass elemClass> : Pat <
169 (vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
170 (elemType elemClass:$z), (elemType elemClass:$w))),
171 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
172 (vecType (IMPLICIT_DEF)), elemClass:$x, sel_x), elemClass:$y, sel_y),
173 elemClass:$z, sel_z), elemClass:$w, sel_w)
176 // bitconvert pattern
177 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
178 (dt (bitconvert (st rc:$src0))),
182 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
183 (vt (AMDGPUdwordaddr (vt rc:$addr))),
187 include "R600Instructions.td"
189 include "SIInstrInfo.td"