1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
39 def COND_EQ : PatLeaf <
41 [{switch(N->get()){{default: return false;
42 case ISD::SETOEQ: case ISD::SETUEQ:
43 case ISD::SETEQ: return true;}}}]
46 def COND_NE : PatLeaf <
48 [{switch(N->get()){{default: return false;
49 case ISD::SETONE: case ISD::SETUNE:
50 case ISD::SETNE: return true;}}}]
52 def COND_GT : PatLeaf <
54 [{switch(N->get()){{default: return false;
55 case ISD::SETOGT: case ISD::SETUGT:
56 case ISD::SETGT: return true;}}}]
59 def COND_GE : PatLeaf <
61 [{switch(N->get()){{default: return false;
62 case ISD::SETOGE: case ISD::SETUGE:
63 case ISD::SETGE: return true;}}}]
66 def COND_LT : PatLeaf <
68 [{switch(N->get()){{default: return false;
69 case ISD::SETOLT: case ISD::SETULT:
70 case ISD::SETLT: return true;}}}]
73 def COND_LE : PatLeaf <
75 [{switch(N->get()){{default: return false;
76 case ISD::SETOLE: case ISD::SETULE:
77 case ISD::SETLE: return true;}}}]
80 def COND_NULL : PatLeaf <
85 //===----------------------------------------------------------------------===//
86 // Load/Store Pattern Fragments
87 //===----------------------------------------------------------------------===//
89 def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
90 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
94 int TWO_PI = 0x40c90fdb;
96 int TWO_PI_INV = 0x3e22f983;
98 def CONST : Constants;
100 def FP_ZERO : PatLeaf <
102 [{return N->getValueAPF().isZero();}]
105 def FP_ONE : PatLeaf <
107 [{return N->isExactlyValue(1.0);}]
110 let isCodeGenOnly = 1, isPseudo = 1 in {
112 let usesCustomInserter = 1 in {
114 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
118 [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
121 class FABS <RegisterClass rc> : AMDGPUShaderInst <
125 [(set rc:$dst, (fabs rc:$src0))]
128 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
132 [(set rc:$dst, (fneg rc:$src0))]
135 } // usesCustomInserter = 1
137 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
138 ComplexPattern addrPat> {
139 def RegisterLoad : AMDGPUShaderInst <
140 (outs dstClass:$dst),
141 (ins addrClass:$addr, i32imm:$chan),
142 "RegisterLoad $dst, $addr",
143 [(set (i32 dstClass:$dst), (AMDGPUregister_load addrPat:$addr,
146 let isRegisterLoad = 1;
149 def RegisterStore : AMDGPUShaderInst <
151 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
152 "RegisterStore $val, $addr",
153 [(AMDGPUregister_store (i32 dstClass:$val), addrPat:$addr, (i32 timm:$chan))]
155 let isRegisterStore = 1;
159 } // End isCodeGenOnly = 1, isPseudo = 1
161 /* Generic helper patterns for intrinsics */
162 /* -------------------------------------- */
164 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
165 RegisterClass rc> : Pat <
166 (fpow rc:$src0, rc:$src1),
167 (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
170 /* Other helper patterns */
171 /* --------------------- */
173 /* Extract element pattern */
174 class Extract_Element <ValueType sub_type, ValueType vec_type,
175 RegisterClass vec_class, int sub_idx,
176 SubRegIndex sub_reg>: Pat<
177 (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
178 (EXTRACT_SUBREG vec_class:$src, sub_reg)
181 /* Insert element pattern */
182 class Insert_Element <ValueType elem_type, ValueType vec_type,
183 RegisterClass elem_class, RegisterClass vec_class,
184 int sub_idx, SubRegIndex sub_reg> : Pat <
186 (vec_type (vector_insert (vec_type vec_class:$vec),
187 (elem_type elem_class:$elem), sub_idx)),
188 (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
191 // Vector Build pattern
192 class Vector1_Build <ValueType vecType, RegisterClass vectorClass,
193 ValueType elemType, RegisterClass elemClass> : Pat <
194 (vecType (build_vector (elemType elemClass:$src))),
195 (vecType elemClass:$src)
198 class Vector2_Build <ValueType vecType, RegisterClass vectorClass,
199 ValueType elemType, RegisterClass elemClass> : Pat <
200 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1))),
201 (INSERT_SUBREG (INSERT_SUBREG
202 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1)
205 class Vector4_Build <ValueType vecType, RegisterClass vectorClass,
206 ValueType elemType, RegisterClass elemClass> : Pat <
207 (vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
208 (elemType elemClass:$z), (elemType elemClass:$w))),
209 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
210 (vecType (IMPLICIT_DEF)), elemClass:$x, sub0), elemClass:$y, sub1),
211 elemClass:$z, sub2), elemClass:$w, sub3)
214 class Vector8_Build <ValueType vecType, RegisterClass vectorClass,
215 ValueType elemType, RegisterClass elemClass> : Pat <
216 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
217 (elemType elemClass:$sub2), (elemType elemClass:$sub3),
218 (elemType elemClass:$sub4), (elemType elemClass:$sub5),
219 (elemType elemClass:$sub6), (elemType elemClass:$sub7))),
220 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
221 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
222 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
223 elemClass:$sub2, sub2), elemClass:$sub3, sub3),
224 elemClass:$sub4, sub4), elemClass:$sub5, sub5),
225 elemClass:$sub6, sub6), elemClass:$sub7, sub7)
228 class Vector16_Build <ValueType vecType, RegisterClass vectorClass,
229 ValueType elemType, RegisterClass elemClass> : Pat <
230 (vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
231 (elemType elemClass:$sub2), (elemType elemClass:$sub3),
232 (elemType elemClass:$sub4), (elemType elemClass:$sub5),
233 (elemType elemClass:$sub6), (elemType elemClass:$sub7),
234 (elemType elemClass:$sub8), (elemType elemClass:$sub9),
235 (elemType elemClass:$sub10), (elemType elemClass:$sub11),
236 (elemType elemClass:$sub12), (elemType elemClass:$sub13),
237 (elemType elemClass:$sub14), (elemType elemClass:$sub15))),
238 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
239 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
240 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
241 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
242 (vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
243 elemClass:$sub2, sub2), elemClass:$sub3, sub3),
244 elemClass:$sub4, sub4), elemClass:$sub5, sub5),
245 elemClass:$sub6, sub6), elemClass:$sub7, sub7),
246 elemClass:$sub8, sub8), elemClass:$sub9, sub9),
247 elemClass:$sub10, sub10), elemClass:$sub11, sub11),
248 elemClass:$sub12, sub12), elemClass:$sub13, sub13),
249 elemClass:$sub14, sub14), elemClass:$sub15, sub15)
252 // bitconvert pattern
253 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
254 (dt (bitconvert (st rc:$src0))),
258 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
259 (vt (AMDGPUdwordaddr (vt rc:$addr))),
263 include "R600Instructions.td"
265 include "SIInstrInfo.td"