1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let isCodeGenOnly = 1;
28 let TSFlags{63} = isRegisterLoad;
29 let TSFlags{62} = isRegisterStore;
32 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
33 : AMDGPUInst<outs, ins, asm, pattern> {
35 field bits<32> Inst = 0xffffffff;
39 def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
40 def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
41 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
43 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
44 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
46 let OperandType = "OPERAND_IMMEDIATE" in {
48 def u32imm : Operand<i32> {
49 let PrintMethod = "printU32ImmOperand";
52 def u16imm : Operand<i16> {
53 let PrintMethod = "printU16ImmOperand";
56 def u8imm : Operand<i8> {
57 let PrintMethod = "printU8ImmOperand";
60 } // End OperandType = "OPERAND_IMMEDIATE"
62 //===--------------------------------------------------------------------===//
64 //===--------------------------------------------------------------------===//
65 def brtarget : Operand<OtherVT>;
67 //===----------------------------------------------------------------------===//
68 // PatLeafs for floating-point comparisons
69 //===----------------------------------------------------------------------===//
71 def COND_OEQ : PatLeaf <
73 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
76 def COND_OGT : PatLeaf <
78 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
81 def COND_OGE : PatLeaf <
83 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
86 def COND_OLT : PatLeaf <
88 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
91 def COND_OLE : PatLeaf <
93 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
96 def COND_UNE : PatLeaf <
98 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
101 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
102 def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
104 //===----------------------------------------------------------------------===//
105 // PatLeafs for unsigned comparisons
106 //===----------------------------------------------------------------------===//
108 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
109 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
110 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
111 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
113 //===----------------------------------------------------------------------===//
114 // PatLeafs for signed comparisons
115 //===----------------------------------------------------------------------===//
117 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
118 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
119 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
120 def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
122 //===----------------------------------------------------------------------===//
123 // PatLeafs for integer equality
124 //===----------------------------------------------------------------------===//
126 def COND_EQ : PatLeaf <
128 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
131 def COND_NE : PatLeaf <
133 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
136 def COND_NULL : PatLeaf <
138 [{(void)N; return false;}]
141 //===----------------------------------------------------------------------===//
142 // Load/Store Pattern Fragments
143 //===----------------------------------------------------------------------===//
145 class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
146 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
149 class PrivateLoad <SDPatternOperator op> : PrivateMemOp <
150 (ops node:$ptr), (op node:$ptr)
153 class PrivateStore <SDPatternOperator op> : PrivateMemOp <
154 (ops node:$value, node:$ptr), (op node:$value, node:$ptr)
157 def extloadi8_private : PrivateLoad <extloadi8>;
158 def sextloadi8_private : PrivateLoad <sextloadi8>;
159 def extloadi16_private : PrivateLoad <extloadi16>;
160 def sextloadi16_private : PrivateLoad <sextloadi16>;
161 def load_private : PrivateLoad <load>;
163 def truncstorei8_private : PrivateStore <truncstorei8>;
164 def truncstorei16_private : PrivateStore <truncstorei16>;
165 def store_private : PrivateStore <store>;
167 def global_store : PatFrag<(ops node:$val, node:$ptr),
168 (store node:$val, node:$ptr), [{
169 return isGlobalStore(dyn_cast<StoreSDNode>(N));
172 // Global address space loads
173 def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
174 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
177 // Constant address space loads
178 def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
179 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
182 def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
183 LoadSDNode *L = cast<LoadSDNode>(N);
184 return L->getExtensionType() == ISD::ZEXTLOAD ||
185 L->getExtensionType() == ISD::EXTLOAD;
188 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
189 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
192 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
193 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
196 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
197 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
200 def az_extloadi8_flat : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
201 return isFlatLoad(dyn_cast<LoadSDNode>(N));
204 def sextloadi8_flat : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
205 return isFlatLoad(dyn_cast<LoadSDNode>(N));
208 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
209 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
212 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
213 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
216 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
217 return isLocalLoad(dyn_cast<LoadSDNode>(N));
220 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
221 return isLocalLoad(dyn_cast<LoadSDNode>(N));
224 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
225 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
228 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
229 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
232 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
233 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
236 def az_extloadi16_flat : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
237 return isFlatLoad(dyn_cast<LoadSDNode>(N));
240 def sextloadi16_flat : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
241 return isFlatLoad(dyn_cast<LoadSDNode>(N));
244 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
245 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
248 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
249 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
252 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
253 return isLocalLoad(dyn_cast<LoadSDNode>(N));
256 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
257 return isLocalLoad(dyn_cast<LoadSDNode>(N));
260 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
261 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
264 def az_extloadi32_global : PatFrag<(ops node:$ptr),
265 (az_extloadi32 node:$ptr), [{
266 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
269 def az_extloadi32_flat : PatFrag<(ops node:$ptr),
270 (az_extloadi32 node:$ptr), [{
271 return isFlatLoad(dyn_cast<LoadSDNode>(N));
274 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
275 (az_extloadi32 node:$ptr), [{
276 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
279 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
280 (truncstorei8 node:$val, node:$ptr), [{
281 return isGlobalStore(dyn_cast<StoreSDNode>(N));
284 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
285 (truncstorei16 node:$val, node:$ptr), [{
286 return isGlobalStore(dyn_cast<StoreSDNode>(N));
289 def truncstorei8_flat : PatFrag<(ops node:$val, node:$ptr),
290 (truncstorei8 node:$val, node:$ptr), [{
291 return isFlatStore(dyn_cast<StoreSDNode>(N));
294 def truncstorei16_flat : PatFrag<(ops node:$val, node:$ptr),
295 (truncstorei16 node:$val, node:$ptr), [{
296 return isFlatStore(dyn_cast<StoreSDNode>(N));
299 def local_store : PatFrag<(ops node:$val, node:$ptr),
300 (store node:$val, node:$ptr), [{
301 return isLocalStore(dyn_cast<StoreSDNode>(N));
304 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
305 (truncstorei8 node:$val, node:$ptr), [{
306 return isLocalStore(dyn_cast<StoreSDNode>(N));
309 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
310 (truncstorei16 node:$val, node:$ptr), [{
311 return isLocalStore(dyn_cast<StoreSDNode>(N));
314 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
315 return isLocalLoad(dyn_cast<LoadSDNode>(N));
318 class Aligned8Bytes <dag ops, dag frag> : PatFrag <ops, frag, [{
319 return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
322 def local_load_aligned8bytes : Aligned8Bytes <
323 (ops node:$ptr), (local_load node:$ptr)
326 def local_store_aligned8bytes : Aligned8Bytes <
327 (ops node:$val, node:$ptr), (local_store node:$val, node:$ptr)
330 class local_binary_atomic_op<SDNode atomic_op> :
331 PatFrag<(ops node:$ptr, node:$value),
332 (atomic_op node:$ptr, node:$value), [{
333 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
337 def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
338 def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
339 def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
340 def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
341 def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
342 def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
343 def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
344 def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
345 def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
346 def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
347 def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
349 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
350 (AMDGPUstore_mskor node:$val, node:$ptr), [{
351 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
355 def atomic_cmp_swap_32_local :
356 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
357 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
358 AtomicSDNode *AN = cast<AtomicSDNode>(N);
359 return AN->getMemoryVT() == MVT::i32 &&
360 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
363 def atomic_cmp_swap_64_local :
364 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
365 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
366 AtomicSDNode *AN = cast<AtomicSDNode>(N);
367 return AN->getMemoryVT() == MVT::i64 &&
368 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
371 def flat_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
372 return isFlatLoad(dyn_cast<LoadSDNode>(N));
375 def flat_store : PatFrag<(ops node:$val, node:$ptr),
376 (store node:$val, node:$ptr), [{
377 return isFlatStore(dyn_cast<StoreSDNode>(N));
380 def mskor_flat : PatFrag<(ops node:$val, node:$ptr),
381 (AMDGPUstore_mskor node:$val, node:$ptr), [{
382 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
385 class global_binary_atomic_op<SDNode atomic_op> : PatFrag<
386 (ops node:$ptr, node:$value),
387 (atomic_op node:$ptr, node:$value),
388 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;}]
391 def atomic_swap_global : global_binary_atomic_op<atomic_swap>;
392 def atomic_add_global : global_binary_atomic_op<atomic_load_add>;
393 def atomic_and_global : global_binary_atomic_op<atomic_load_and>;
394 def atomic_max_global : global_binary_atomic_op<atomic_load_max>;
395 def atomic_min_global : global_binary_atomic_op<atomic_load_min>;
396 def atomic_or_global : global_binary_atomic_op<atomic_load_or>;
397 def atomic_sub_global : global_binary_atomic_op<atomic_load_sub>;
398 def atomic_umax_global : global_binary_atomic_op<atomic_load_umax>;
399 def atomic_umin_global : global_binary_atomic_op<atomic_load_umin>;
400 def atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
402 //===----------------------------------------------------------------------===//
403 // Misc Pattern Fragments
404 //===----------------------------------------------------------------------===//
407 (ops node:$src0, node:$src1, node:$src2),
408 (fadd (fmul node:$src0, node:$src1), node:$src2)
412 int TWO_PI = 0x40c90fdb;
414 int TWO_PI_INV = 0x3e22f983;
415 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
416 int FP32_NEG_ONE = 0xbf800000;
417 int FP32_ONE = 0x3f800000;
419 def CONST : Constants;
421 def FP_ZERO : PatLeaf <
423 [{return N->getValueAPF().isZero();}]
426 def FP_ONE : PatLeaf <
428 [{return N->isExactlyValue(1.0);}]
431 let isCodeGenOnly = 1, isPseudo = 1 in {
433 let usesCustomInserter = 1 in {
435 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
439 [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
442 class FABS <RegisterClass rc> : AMDGPUShaderInst <
446 [(set f32:$dst, (fabs f32:$src0))]
449 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
453 [(set f32:$dst, (fneg f32:$src0))]
456 } // usesCustomInserter = 1
458 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
459 ComplexPattern addrPat> {
460 let UseNamedOperandTable = 1 in {
462 def RegisterLoad : AMDGPUShaderInst <
463 (outs dstClass:$dst),
464 (ins addrClass:$addr, i32imm:$chan),
465 "RegisterLoad $dst, $addr",
466 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
468 let isRegisterLoad = 1;
471 def RegisterStore : AMDGPUShaderInst <
473 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
474 "RegisterStore $val, $addr",
475 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
477 let isRegisterStore = 1;
482 } // End isCodeGenOnly = 1, isPseudo = 1
484 /* Generic helper patterns for intrinsics */
485 /* -------------------------------------- */
487 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
489 (fpow f32:$src0, f32:$src1),
490 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
493 /* Other helper patterns */
494 /* --------------------- */
496 /* Extract element pattern */
497 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
500 (sub_type (vector_extract vec_type:$src, sub_idx)),
501 (EXTRACT_SUBREG $src, sub_reg)
504 /* Insert element pattern */
505 class Insert_Element <ValueType elem_type, ValueType vec_type,
506 int sub_idx, SubRegIndex sub_reg>
508 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
509 (INSERT_SUBREG $vec, $elem, sub_reg)
512 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
513 // can handle COPY instructions.
514 // bitconvert pattern
515 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
516 (dt (bitconvert (st rc:$src0))),
520 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
521 // can handle COPY instructions.
522 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
523 (vt (AMDGPUdwordaddr (vt rc:$addr))),
529 multiclass BFIPatterns <Instruction BFI_INT,
530 Instruction LoadImm32,
531 RegisterClass RC64> {
532 // Definition from ISA doc:
533 // (y & x) | (z & ~x)
535 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
539 // SHA-256 Ch function
542 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
547 (fcopysign f32:$src0, f32:$src1),
548 (BFI_INT (LoadImm32 0x7fffffff), $src0, $src1)
552 (f64 (fcopysign f64:$src0, f64:$src1)),
554 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
555 (BFI_INT (LoadImm32 0x7fffffff),
556 (i32 (EXTRACT_SUBREG $src0, sub1)),
557 (i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
561 // SHA-256 Ma patterns
563 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
564 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
565 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
566 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
569 // Bitfield extract patterns
573 XXX: The BFE pattern is not working correctly because the XForm is not being
576 def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
577 def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
578 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
580 class BFEPattern <Instruction BFE> : Pat <
581 (and (srl i32:$x, legalshift32:$y), bfemask:$z),
588 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
589 (rotr i32:$src0, i32:$src1),
590 (BIT_ALIGN $src0, $src0, $src1)
593 // 24-bit arithmetic patterns
594 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
597 class UMUL24Pattern <Instruction UMUL24> : Pat <
598 (mul U24:$x, U24:$y),
603 class IMad24Pat<Instruction Inst> : Pat <
604 (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
605 (Inst $src0, $src1, $src2)
608 class UMad24Pat<Instruction Inst> : Pat <
609 (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
610 (Inst $src0, $src1, $src2)
613 multiclass Expand24IBitOps<Instruction MulInst, Instruction AddInst> {
614 def _expand_imad24 : Pat <
615 (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
616 (AddInst (MulInst $src0, $src1), $src2)
619 def _expand_imul24 : Pat <
620 (AMDGPUmul_i24 i32:$src0, i32:$src1),
621 (MulInst $src0, $src1)
625 multiclass Expand24UBitOps<Instruction MulInst, Instruction AddInst> {
626 def _expand_umad24 : Pat <
627 (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
628 (AddInst (MulInst $src0, $src1), $src2)
631 def _expand_umul24 : Pat <
632 (AMDGPUmul_u24 i32:$src0, i32:$src1),
633 (MulInst $src0, $src1)
637 class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
638 (fdiv FP_ONE, vt:$src),
642 multiclass RsqPat<Instruction RsqInst, ValueType vt> {
644 (fdiv FP_ONE, (fsqrt vt:$src)),
649 (AMDGPUrcp (fsqrt vt:$src)),
654 include "R600Instructions.td"
655 include "R700Instructions.td"
656 include "EvergreenInstructions.td"
657 include "CaymanInstructions.td"
659 include "SIInstrInfo.td"