1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
13 //===----------------------------------------------------------------------===//
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "InstPrinter/AMDGPUInstPrinter.h"
20 #include "R600InstrInfo.h"
21 #include "SIInstrInfo.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/GlobalVariable.h"
26 #include "llvm/MC/MCCodeEmitter.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCObjectStreamer.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/Format.h"
38 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
42 enum AMDGPUMCInstLower::SISubtarget
43 AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
46 return AMDGPUMCInstLower::SI;
47 case AMDGPUSubtarget::VOLCANIC_ISLANDS:
48 return AMDGPUMCInstLower::VI;
52 unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {
54 int MCOpcode = AMDGPU::getMCOpcode(MIOpcode,
55 AMDGPUSubtargetToSISubtarget(ST.getGeneration()));
62 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
64 OutMI.setOpcode(getMCOpcode(MI->getOpcode()));
66 for (const MachineOperand &MO : MI->explicit_operands()) {
68 switch (MO.getType()) {
70 llvm_unreachable("unknown operand type");
71 case MachineOperand::MO_Immediate:
72 MCOp = MCOperand::CreateImm(MO.getImm());
74 case MachineOperand::MO_Register:
75 MCOp = MCOperand::CreateReg(MO.getReg());
77 case MachineOperand::MO_MachineBasicBlock:
78 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
79 MO.getMBB()->getSymbol(), Ctx));
81 case MachineOperand::MO_GlobalAddress: {
82 const GlobalValue *GV = MO.getGlobal();
83 MCSymbol *Sym = Ctx.GetOrCreateSymbol(StringRef(GV->getName()));
84 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(Sym, Ctx));
87 case MachineOperand::MO_TargetIndex: {
88 assert(MO.getIndex() == AMDGPU::TI_CONSTDATA_START);
89 MCSymbol *Sym = Ctx.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
90 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::Create(Sym, Ctx);
91 MCOp = MCOperand::CreateExpr(Expr);
95 OutMI.addOperand(MCOp);
99 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
100 AMDGPUMCInstLower MCInstLowering(OutContext,
101 MF->getTarget().getSubtarget<AMDGPUSubtarget>());
105 if (!TM.getSubtargetImpl()->getInstrInfo()->verifyInstruction(MI, Err)) {
106 errs() << "Warning: Illegal instruction detected: " << Err << "\n";
110 if (MI->isBundle()) {
111 const MachineBasicBlock *MBB = MI->getParent();
112 MachineBasicBlock::const_instr_iterator I = MI;
114 while (I != MBB->end() && I->isInsideBundle()) {
120 MCInstLowering.lower(MI, TmpInst);
121 EmitToStreamer(OutStreamer, TmpInst);
124 // Disassemble instruction/operands to text.
125 DisasmLines.resize(DisasmLines.size() + 1);
126 std::string &DisasmLine = DisasmLines.back();
127 raw_string_ostream DisasmStream(DisasmLine);
129 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
130 *TM.getSubtargetImpl()->getInstrInfo(),
131 *TM.getSubtargetImpl()->getRegisterInfo());
132 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef());
134 // Disassemble instruction/operands to hex representation.
135 SmallVector<MCFixup, 4> Fixups;
136 SmallVector<char, 16> CodeBytes;
137 raw_svector_ostream CodeStream(CodeBytes);
139 MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
140 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
141 InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
142 TM.getSubtarget<MCSubtargetInfo>());
145 HexLines.resize(HexLines.size() + 1);
146 std::string &HexLine = HexLines.back();
147 raw_string_ostream HexStream(HexLine);
149 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
150 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
151 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
154 DisasmStream.flush();
155 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());