1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPURegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
20 AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
21 const TargetInstrInfo &tii)
22 : AMDGPUGenRegisterInfo(0),
27 //===----------------------------------------------------------------------===//
28 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
29 // they are not supported at this time.
30 //===----------------------------------------------------------------------===//
32 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
34 const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
36 return &CalleeSavedReg;
39 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
41 unsigned FIOperandNum,
42 RegScavenger *RS) const {
43 assert(!"Subroutines not supported yet");
46 unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
47 assert(!"Subroutines not supported yet");
51 unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
53 switch(IndirectIndex) {
54 case 0: return AMDGPU::sub0;
55 case 1: return AMDGPU::sub1;
56 case 2: return AMDGPU::sub2;
57 case 3: return AMDGPU::sub3;
58 case 4: return AMDGPU::sub4;
59 case 5: return AMDGPU::sub5;
60 case 6: return AMDGPU::sub6;
61 case 7: return AMDGPU::sub7;
62 case 8: return AMDGPU::sub8;
63 case 9: return AMDGPU::sub9;
64 case 10: return AMDGPU::sub10;
65 case 11: return AMDGPU::sub11;
66 case 12: return AMDGPU::sub12;
67 case 13: return AMDGPU::sub13;
68 case 14: return AMDGPU::sub14;
69 case 15: return AMDGPU::sub15;
70 default: llvm_unreachable("indirect index out of range");
74 #define GET_REGINFO_TARGET_DESC
75 #include "AMDGPUGenRegisterInfo.inc"