1 //===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief TargetRegisterInfo interface that is implemented by all hw codegen
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUREGISTERINFO_H
17 #define AMDGPUREGISTERINFO_H
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
22 #define GET_REGINFO_HEADER
23 #define GET_REGINFO_ENUM
24 #include "AMDGPUGenRegisterInfo.inc"
28 class AMDGPUTargetMachine;
29 class TargetInstrInfo;
31 struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
33 static const uint16_t CalleeSavedReg;
35 AMDGPURegisterInfo(TargetMachine &tm);
37 virtual BitVector getReservedRegs(const MachineFunction &MF) const {
38 assert(!"Unimplemented"); return BitVector();
41 /// \param RC is an AMDIL reg class.
43 /// \returns The ISA reg class that is equivalent to \p RC.
44 virtual const TargetRegisterClass * getISARegClass(
45 const TargetRegisterClass * RC) const {
46 assert(!"Unimplemented"); return NULL;
49 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
50 assert(!"Unimplemented"); return NULL;
53 const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;
54 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
55 unsigned FIOperandNum,
56 RegScavenger *RS) const;
57 unsigned getFrameRegister(const MachineFunction &MF) const;
59 unsigned getIndirectSubReg(unsigned IndirectIndex) const;
63 } // End namespace llvm
65 #endif // AMDIDSAREGISTERINFO_H