1 //===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief TargetRegisterInfo interface that is implemented by all hw codegen
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
22 #define GET_REGINFO_HEADER
23 #define GET_REGINFO_ENUM
24 #include "AMDGPUGenRegisterInfo.inc"
28 class AMDGPUSubtarget;
29 class TargetInstrInfo;
31 struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
32 static const MCPhysReg CalleeSavedReg;
33 const AMDGPUSubtarget &ST;
35 AMDGPURegisterInfo(const AMDGPUSubtarget &st);
37 BitVector getReservedRegs(const MachineFunction &MF) const override {
38 assert(!"Unimplemented"); return BitVector();
41 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
42 assert(!"Unimplemented"); return nullptr;
45 virtual unsigned getHWRegIndex(unsigned Reg) const {
46 assert(!"Unimplemented"); return 0;
49 /// \returns the sub reg enum value for the given \p Channel
50 /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
51 unsigned getSubRegFromChannel(unsigned Channel) const;
53 const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
54 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
55 unsigned FIOperandNum,
56 RegScavenger *RS) const override;
57 unsigned getFrameRegister(const MachineFunction &MF) const override;
59 unsigned getIndirectSubReg(unsigned IndirectIndex) const;
63 } // End namespace llvm