1 //===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Tablegen register definitions common to all hw codegen targets.
12 //===----------------------------------------------------------------------===//
14 let Namespace = "AMDGPU" in {
16 foreach Index = 0-15 in {
17 def sub#Index : SubRegIndex;
20 def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
24 include "R600RegisterInfo.td"
25 include "SIRegisterInfo.td"