1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIISelLowering.h"
20 #include "SIInstrInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/ADT/SmallString.h"
26 #define DEBUG_TYPE "amdgpu-subtarget"
28 #define GET_SUBTARGETINFO_ENUM
29 #define GET_SUBTARGETINFO_TARGET_DESC
30 #define GET_SUBTARGETINFO_CTOR
31 #include "AMDGPUGenSubtargetInfo.inc"
34 AMDGPUSubtarget::initializeSubtargetDependencies(StringRef GPU, StringRef FS) {
35 // Determine default and user-specified characteristics
36 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
37 // enabled, but some instructions do not respect them and they run at the
38 // double precision rate, so don't enable by default.
40 // We want to be able to turn these off, but making this a subtarget feature
41 // for SI has the unhelpful behavior that it unsets everything else if you
44 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
47 ParseSubtargetFeatures(GPU, FullFS);
49 // FIXME: I don't think think Evergreen has any useful support for
50 // denormals, but should be checked. Should we issue a warning somewhere
51 // if someone tries to enable these?
52 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
53 FP32Denormals = false;
54 FP64Denormals = false;
59 static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
60 std::string Ret = "e-p:32:32";
63 // 32-bit private, local, and region pointers. 64-bit global and constant.
64 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
67 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
68 "-v512:512-v1024:1024-v2048:2048-n32:64";
73 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
75 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
76 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
77 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
78 FP64Denormals(false), FP32Denormals(false), CaymanISA(false),
79 FlatAddressSpace(false), EnableIRStructurizer(true),
80 EnablePromoteAlloca(false), EnableIfCvt(true),
81 EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
82 EnableVGPRSpilling(false),
83 DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),
84 FrameLowering(TargetFrameLowering::StackGrowsUp,
85 64 * 16, // Maximum stack alignment (long16)
87 InstrItins(getInstrItineraryForCPU(GPU)),
89 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
90 InstrInfo.reset(new R600InstrInfo(*this));
91 TLInfo.reset(new R600TargetLowering(TM));
93 InstrInfo.reset(new SIInstrInfo(*this));
94 TLInfo.reset(new SITargetLowering(TM));
98 unsigned AMDGPUSubtarget::getStackEntrySize() const {
99 assert(getGeneration() <= NORTHERN_ISLANDS);
100 switch(getWavefrontSize()) {
104 return hasCaymanISA() ? 4 : 8;
108 llvm_unreachable("Illegal wavefront size.");
112 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
113 switch(getGeneration()) {
114 default: llvm_unreachable("ChipID unknown");
115 case SEA_ISLANDS: return 12;
119 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
120 const SIMachineFunctionInfo *MFI) const {
121 return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;