1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
53 short TexVTXClauseSize;
60 bool FlatAddressSpace;
61 bool EnableIRStructurizer;
62 bool EnablePromoteAlloca;
64 bool EnableLoadStoreOpt;
65 unsigned WavefrontSize;
68 bool EnableVGPRSpilling;
70 AMDGPUFrameLowering FrameLowering;
71 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
72 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
73 InstrItineraryData InstrItins;
77 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
78 AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU,
81 const AMDGPUFrameLowering *getFrameLowering() const override {
82 return &FrameLowering;
84 const AMDGPUInstrInfo *getInstrInfo() const override {
85 return InstrInfo.get();
87 const AMDGPURegisterInfo *getRegisterInfo() const override {
88 return &InstrInfo->getRegisterInfo();
90 AMDGPUTargetLowering *getTargetLowering() const override {
93 const InstrItineraryData *getInstrItineraryData() const override {
97 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
99 bool is64bit() const {
103 bool hasVertexCache() const {
104 return HasVertexCache;
107 short getTexVTXClauseSize() const {
108 return TexVTXClauseSize;
111 Generation getGeneration() const {
115 bool hasHWFP64() const {
119 bool hasCaymanISA() const {
123 bool hasFP32Denormals() const {
124 return FP32Denormals;
127 bool hasFP64Denormals() const {
128 return FP64Denormals;
131 bool hasFastFMAF32() const {
135 bool hasFlatAddressSpace() const {
136 return FlatAddressSpace;
139 bool hasBFE() const {
140 return (getGeneration() >= EVERGREEN);
143 bool hasBFI() const {
144 return (getGeneration() >= EVERGREEN);
147 bool hasBFM() const {
151 bool hasBCNT(unsigned Size) const {
153 return (getGeneration() >= EVERGREEN);
156 return (getGeneration() >= SOUTHERN_ISLANDS);
161 bool hasMulU24() const {
162 return (getGeneration() >= EVERGREEN);
165 bool hasMulI24() const {
166 return (getGeneration() >= SOUTHERN_ISLANDS ||
170 bool hasFFBL() const {
171 return (getGeneration() >= EVERGREEN);
174 bool hasFFBH() const {
175 return (getGeneration() >= EVERGREEN);
178 bool IsIRStructurizerEnabled() const {
179 return EnableIRStructurizer;
182 bool isPromoteAllocaEnabled() const {
183 return EnablePromoteAlloca;
186 bool isIfCvtEnabled() const {
190 bool loadStoreOptEnabled() const {
191 return EnableLoadStoreOpt;
194 unsigned getWavefrontSize() const {
195 return WavefrontSize;
198 unsigned getStackEntrySize() const;
200 bool hasCFAluBug() const {
201 assert(getGeneration() <= NORTHERN_ISLANDS);
205 int getLocalMemorySize() const {
206 return LocalMemorySize;
209 unsigned getAmdKernelCodeChipID() const;
211 bool enableMachineScheduler() const override {
215 void overrideSchedPolicy(MachineSchedPolicy &Policy,
216 MachineInstr *begin, MachineInstr *end,
217 unsigned NumRegionInstrs) const override;
219 // Helper functions to simplify if statements
220 bool isTargetELF() const {
224 StringRef getDeviceName() const {
228 bool dumpCode() const {
231 bool r600ALUEncoding() const {
234 bool isAmdHsaOS() const {
235 return TargetTriple.getOS() == Triple::AMDHSA;
237 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
239 unsigned getMaxWavesPerCU() const {
240 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
243 // FIXME: Not sure what this is for other subtagets.
244 llvm_unreachable("do not know max waves per CU for this subtarget.");
248 } // End namespace llvm