1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
57 short TexVTXClauseSize;
64 bool FlatAddressSpace;
65 bool EnableIRStructurizer;
66 bool EnablePromoteAlloca;
68 bool EnableLoadStoreOpt;
69 unsigned WavefrontSize;
72 bool EnableVGPRSpilling;
75 AMDGPUFrameLowering FrameLowering;
76 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
77 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
78 InstrItineraryData InstrItins;
82 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
83 AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU,
86 const AMDGPUFrameLowering *getFrameLowering() const override {
87 return &FrameLowering;
89 const AMDGPUInstrInfo *getInstrInfo() const override {
90 return InstrInfo.get();
92 const AMDGPURegisterInfo *getRegisterInfo() const override {
93 return &InstrInfo->getRegisterInfo();
95 AMDGPUTargetLowering *getTargetLowering() const override {
98 const InstrItineraryData *getInstrItineraryData() const override {
102 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
104 bool is64bit() const {
108 bool hasVertexCache() const {
109 return HasVertexCache;
112 short getTexVTXClauseSize() const {
113 return TexVTXClauseSize;
116 Generation getGeneration() const {
120 bool hasHWFP64() const {
124 bool hasCaymanISA() const {
128 bool hasFP32Denormals() const {
129 return FP32Denormals;
132 bool hasFP64Denormals() const {
133 return FP64Denormals;
136 bool hasFastFMAF32() const {
140 bool hasFlatAddressSpace() const {
141 return FlatAddressSpace;
144 bool hasBFE() const {
145 return (getGeneration() >= EVERGREEN);
148 bool hasBFI() const {
149 return (getGeneration() >= EVERGREEN);
152 bool hasBFM() const {
156 bool hasBCNT(unsigned Size) const {
158 return (getGeneration() >= EVERGREEN);
161 return (getGeneration() >= SOUTHERN_ISLANDS);
166 bool hasMulU24() const {
167 return (getGeneration() >= EVERGREEN);
170 bool hasMulI24() const {
171 return (getGeneration() >= SOUTHERN_ISLANDS ||
175 bool hasFFBL() const {
176 return (getGeneration() >= EVERGREEN);
179 bool hasFFBH() const {
180 return (getGeneration() >= EVERGREEN);
183 bool IsIRStructurizerEnabled() const {
184 return EnableIRStructurizer;
187 bool isPromoteAllocaEnabled() const {
188 return EnablePromoteAlloca;
191 bool isIfCvtEnabled() const {
195 bool loadStoreOptEnabled() const {
196 return EnableLoadStoreOpt;
199 unsigned getWavefrontSize() const {
200 return WavefrontSize;
203 unsigned getStackEntrySize() const;
205 bool hasCFAluBug() const {
206 assert(getGeneration() <= NORTHERN_ISLANDS);
210 int getLocalMemorySize() const {
211 return LocalMemorySize;
214 bool hasSGPRInitBug() const {
218 unsigned getAmdKernelCodeChipID() const;
220 bool enableMachineScheduler() const override {
224 void overrideSchedPolicy(MachineSchedPolicy &Policy,
225 MachineInstr *begin, MachineInstr *end,
226 unsigned NumRegionInstrs) const override;
228 // Helper functions to simplify if statements
229 bool isTargetELF() const {
233 StringRef getDeviceName() const {
237 bool dumpCode() const {
240 bool r600ALUEncoding() const {
243 bool isAmdHsaOS() const {
244 return TargetTriple.getOS() == Triple::AMDHSA;
246 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
248 unsigned getMaxWavesPerCU() const {
249 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
252 // FIXME: Not sure what this is for other subtagets.
253 llvm_unreachable("do not know max waves per CU for this subtarget.");
256 bool enableSubRegLiveness() const override {
261 } // End namespace llvm