1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
57 short TexVTXClauseSize;
64 bool FlatAddressSpace;
65 bool EnableIRStructurizer;
66 bool EnablePromoteAlloca;
68 bool EnableLoadStoreOpt;
69 unsigned WavefrontSize;
72 bool EnableVGPRSpilling;
80 AMDGPUFrameLowering FrameLowering;
81 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
82 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
83 InstrItineraryData InstrItins;
87 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
88 AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU,
91 const AMDGPUFrameLowering *getFrameLowering() const override {
92 return &FrameLowering;
94 const AMDGPUInstrInfo *getInstrInfo() const override {
95 return InstrInfo.get();
97 const AMDGPURegisterInfo *getRegisterInfo() const override {
98 return &InstrInfo->getRegisterInfo();
100 AMDGPUTargetLowering *getTargetLowering() const override {
103 const InstrItineraryData *getInstrItineraryData() const override {
107 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
109 bool is64bit() const {
113 bool hasVertexCache() const {
114 return HasVertexCache;
117 short getTexVTXClauseSize() const {
118 return TexVTXClauseSize;
121 Generation getGeneration() const {
125 bool hasHWFP64() const {
129 bool hasCaymanISA() const {
133 bool hasFP32Denormals() const {
134 return FP32Denormals;
137 bool hasFP64Denormals() const {
138 return FP64Denormals;
141 bool hasFastFMAF32() const {
145 bool hasFlatAddressSpace() const {
146 return FlatAddressSpace;
149 bool hasBFE() const {
150 return (getGeneration() >= EVERGREEN);
153 bool hasBFI() const {
154 return (getGeneration() >= EVERGREEN);
157 bool hasBFM() const {
161 bool hasBCNT(unsigned Size) const {
163 return (getGeneration() >= EVERGREEN);
166 return (getGeneration() >= SOUTHERN_ISLANDS);
171 bool hasMulU24() const {
172 return (getGeneration() >= EVERGREEN);
175 bool hasMulI24() const {
176 return (getGeneration() >= SOUTHERN_ISLANDS ||
180 bool hasFFBL() const {
181 return (getGeneration() >= EVERGREEN);
184 bool hasFFBH() const {
185 return (getGeneration() >= EVERGREEN);
188 bool hasCARRY() const {
189 return (getGeneration() >= EVERGREEN);
192 bool hasBORROW() const {
193 return (getGeneration() >= EVERGREEN);
196 bool IsIRStructurizerEnabled() const {
197 return EnableIRStructurizer;
200 bool isPromoteAllocaEnabled() const {
201 return EnablePromoteAlloca;
204 bool isIfCvtEnabled() const {
208 bool loadStoreOptEnabled() const {
209 return EnableLoadStoreOpt;
212 unsigned getWavefrontSize() const {
213 return WavefrontSize;
216 unsigned getStackEntrySize() const;
218 bool hasCFAluBug() const {
219 assert(getGeneration() <= NORTHERN_ISLANDS);
223 int getLocalMemorySize() const {
224 return LocalMemorySize;
227 bool hasSGPRInitBug() const {
231 unsigned getAmdKernelCodeChipID() const;
233 bool enableMachineScheduler() const override {
237 void overrideSchedPolicy(MachineSchedPolicy &Policy,
238 MachineInstr *begin, MachineInstr *end,
239 unsigned NumRegionInstrs) const override;
241 // Helper functions to simplify if statements
242 bool isTargetELF() const {
246 StringRef getDeviceName() const {
250 bool dumpCode() const {
253 bool r600ALUEncoding() const {
256 bool isAmdHsaOS() const {
257 return TargetTriple.getOS() == Triple::AMDHSA;
259 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
261 unsigned getMaxWavesPerCU() const {
262 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
265 // FIXME: Not sure what this is for other subtagets.
266 llvm_unreachable("do not know max waves per CU for this subtarget.");
269 bool enableSubRegLiveness() const override {
274 } // End namespace llvm