1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
57 short TexVTXClauseSize;
64 bool FlatAddressSpace;
65 bool EnableIRStructurizer;
66 bool EnablePromoteAlloca;
68 bool EnableLoadStoreOpt;
69 unsigned WavefrontSize;
72 bool EnableVGPRSpilling;
81 AMDGPUFrameLowering FrameLowering;
82 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
83 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
84 InstrItineraryData InstrItins;
88 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
89 AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU,
92 const AMDGPUFrameLowering *getFrameLowering() const override {
93 return &FrameLowering;
95 const AMDGPUInstrInfo *getInstrInfo() const override {
96 return InstrInfo.get();
98 const AMDGPURegisterInfo *getRegisterInfo() const override {
99 return &InstrInfo->getRegisterInfo();
101 AMDGPUTargetLowering *getTargetLowering() const override {
104 const InstrItineraryData *getInstrItineraryData() const override {
108 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
110 bool is64bit() const {
114 bool hasVertexCache() const {
115 return HasVertexCache;
118 short getTexVTXClauseSize() const {
119 return TexVTXClauseSize;
122 Generation getGeneration() const {
126 bool hasHWFP64() const {
130 bool hasCaymanISA() const {
134 bool hasFP32Denormals() const {
135 return FP32Denormals;
138 bool hasFP64Denormals() const {
139 return FP64Denormals;
142 bool hasFastFMAF32() const {
146 bool hasFlatAddressSpace() const {
147 return FlatAddressSpace;
150 bool hasBFE() const {
151 return (getGeneration() >= EVERGREEN);
154 bool hasBFI() const {
155 return (getGeneration() >= EVERGREEN);
158 bool hasBFM() const {
162 bool hasBCNT(unsigned Size) const {
164 return (getGeneration() >= EVERGREEN);
167 return (getGeneration() >= SOUTHERN_ISLANDS);
172 bool hasMulU24() const {
173 return (getGeneration() >= EVERGREEN);
176 bool hasMulI24() const {
177 return (getGeneration() >= SOUTHERN_ISLANDS ||
181 bool hasFFBL() const {
182 return (getGeneration() >= EVERGREEN);
185 bool hasFFBH() const {
186 return (getGeneration() >= EVERGREEN);
189 bool hasCARRY() const {
190 return (getGeneration() >= EVERGREEN);
193 bool hasBORROW() const {
194 return (getGeneration() >= EVERGREEN);
197 bool IsIRStructurizerEnabled() const {
198 return EnableIRStructurizer;
201 bool isPromoteAllocaEnabled() const {
202 return EnablePromoteAlloca;
205 bool isIfCvtEnabled() const {
209 bool loadStoreOptEnabled() const {
210 return EnableLoadStoreOpt;
213 unsigned getWavefrontSize() const {
214 return WavefrontSize;
217 unsigned getStackEntrySize() const;
219 bool hasCFAluBug() const {
220 assert(getGeneration() <= NORTHERN_ISLANDS);
224 int getLocalMemorySize() const {
225 return LocalMemorySize;
228 bool hasSGPRInitBug() const {
232 int getLDSBankCount() const {
236 unsigned getAmdKernelCodeChipID() const;
238 bool enableMachineScheduler() const override {
242 void overrideSchedPolicy(MachineSchedPolicy &Policy,
243 MachineInstr *begin, MachineInstr *end,
244 unsigned NumRegionInstrs) const override;
246 // Helper functions to simplify if statements
247 bool isTargetELF() const {
251 StringRef getDeviceName() const {
255 bool dumpCode() const {
258 bool r600ALUEncoding() const {
261 bool isAmdHsaOS() const {
262 return TargetTriple.getOS() == Triple::AMDHSA;
264 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
266 unsigned getMaxWavesPerCU() const {
267 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
270 // FIXME: Not sure what this is for other subtagets.
271 llvm_unreachable("do not know max waves per CU for this subtarget.");
274 bool enableSubRegLiveness() const override {
279 } // End namespace llvm