1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
57 short TexVTXClauseSize;
64 bool FlatAddressSpace;
65 bool EnableIRStructurizer;
66 bool EnablePromoteAlloca;
68 bool EnableLoadStoreOpt;
69 unsigned WavefrontSize;
72 bool EnableVGPRSpilling;
78 AMDGPUFrameLowering FrameLowering;
79 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
80 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
81 InstrItineraryData InstrItins;
85 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
86 AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU,
89 const AMDGPUFrameLowering *getFrameLowering() const override {
90 return &FrameLowering;
92 const AMDGPUInstrInfo *getInstrInfo() const override {
93 return InstrInfo.get();
95 const AMDGPURegisterInfo *getRegisterInfo() const override {
96 return &InstrInfo->getRegisterInfo();
98 AMDGPUTargetLowering *getTargetLowering() const override {
101 const InstrItineraryData *getInstrItineraryData() const override {
105 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
107 bool is64bit() const {
111 bool hasVertexCache() const {
112 return HasVertexCache;
115 short getTexVTXClauseSize() const {
116 return TexVTXClauseSize;
119 Generation getGeneration() const {
123 bool hasHWFP64() const {
127 bool hasCaymanISA() const {
131 bool hasFP32Denormals() const {
132 return FP32Denormals;
135 bool hasFP64Denormals() const {
136 return FP64Denormals;
139 bool hasFastFMAF32() const {
143 bool hasFlatAddressSpace() const {
144 return FlatAddressSpace;
147 bool hasBFE() const {
148 return (getGeneration() >= EVERGREEN);
151 bool hasBFI() const {
152 return (getGeneration() >= EVERGREEN);
155 bool hasBFM() const {
159 bool hasBCNT(unsigned Size) const {
161 return (getGeneration() >= EVERGREEN);
164 return (getGeneration() >= SOUTHERN_ISLANDS);
169 bool hasMulU24() const {
170 return (getGeneration() >= EVERGREEN);
173 bool hasMulI24() const {
174 return (getGeneration() >= SOUTHERN_ISLANDS ||
178 bool hasFFBL() const {
179 return (getGeneration() >= EVERGREEN);
182 bool hasFFBH() const {
183 return (getGeneration() >= EVERGREEN);
186 bool IsIRStructurizerEnabled() const {
187 return EnableIRStructurizer;
190 bool isPromoteAllocaEnabled() const {
191 return EnablePromoteAlloca;
194 bool isIfCvtEnabled() const {
198 bool loadStoreOptEnabled() const {
199 return EnableLoadStoreOpt;
202 unsigned getWavefrontSize() const {
203 return WavefrontSize;
206 unsigned getStackEntrySize() const;
208 bool hasCFAluBug() const {
209 assert(getGeneration() <= NORTHERN_ISLANDS);
213 int getLocalMemorySize() const {
214 return LocalMemorySize;
217 bool hasSGPRInitBug() const {
221 unsigned getAmdKernelCodeChipID() const;
223 bool enableMachineScheduler() const override {
227 void overrideSchedPolicy(MachineSchedPolicy &Policy,
228 MachineInstr *begin, MachineInstr *end,
229 unsigned NumRegionInstrs) const override;
231 // Helper functions to simplify if statements
232 bool isTargetELF() const {
236 StringRef getDeviceName() const {
240 bool dumpCode() const {
243 bool r600ALUEncoding() const {
246 bool isAmdHsaOS() const {
247 return TargetTriple.getOS() == Triple::AMDHSA;
249 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
251 unsigned getMaxWavesPerCU() const {
252 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
255 // FIXME: Not sure what this is for other subtagets.
256 llvm_unreachable("do not know max waves per CU for this subtarget.");
259 bool enableSubRegLiveness() const override {
264 } // End namespace llvm