1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "AMDGPUTargetTransformInfo.h"
19 #include "R600ISelLowering.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineScheduler.h"
22 #include "SIISelLowering.h"
23 #include "SIInstrInfo.h"
24 #include "llvm/Analysis/Passes.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_os_ostream.h"
34 #include "llvm/Transforms/IPO.h"
35 #include "llvm/Transforms/Scalar.h"
36 #include <llvm/CodeGen/Passes.h>
40 extern "C" void LLVMInitializeR600Target() {
41 // Register the target
42 RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
43 RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
46 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
47 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
50 static MachineSchedRegistry
51 SchedCustomRegistry("r600", "Run R600's custom scheduler",
52 createR600MachineScheduler);
54 static std::string computeDataLayout(StringRef TT) {
56 std::string Ret = "e-p:32:32";
58 if (Triple.getArch() == Triple::amdgcn) {
59 // 32-bit private, local, and region pointers. 64-bit global and constant.
60 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
63 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
64 "-v512:512-v1024:1024-v2048:2048-n32:64";
69 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
70 StringRef CPU, StringRef FS,
71 TargetOptions Options, Reloc::Model RM,
73 CodeGenOpt::Level OptLevel)
74 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
75 DL(computeDataLayout(TT)),
76 TLOF(new TargetLoweringObjectFileELF()),
77 Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
78 setRequiresStructuredCFG(true);
82 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
86 //===----------------------------------------------------------------------===//
87 // R600 Target Machine (R600 -> Cayman)
88 //===----------------------------------------------------------------------===//
90 R600TargetMachine::R600TargetMachine(const Target &T, StringRef TT, StringRef FS,
91 StringRef CPU, TargetOptions Options, Reloc::Model RM,
92 CodeModel::Model CM, CodeGenOpt::Level OL) :
93 AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) { }
96 //===----------------------------------------------------------------------===//
97 // GCN Target Machine (SI+)
98 //===----------------------------------------------------------------------===//
100 GCNTargetMachine::GCNTargetMachine(const Target &T, StringRef TT, StringRef FS,
101 StringRef CPU, TargetOptions Options, Reloc::Model RM,
102 CodeModel::Model CM, CodeGenOpt::Level OL) :
103 AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) { }
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
110 class AMDGPUPassConfig : public TargetPassConfig {
112 AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
113 : TargetPassConfig(TM, PM) {}
115 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
116 return getTM<AMDGPUTargetMachine>();
120 createMachineScheduler(MachineSchedContext *C) const override {
121 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
122 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
123 return createR600MachineScheduler(C);
127 void addIRPasses() override;
128 void addCodeGenPrepare() override;
129 virtual bool addPreISel() override;
130 virtual bool addInstSelector() override;
133 class R600PassConfig : public AMDGPUPassConfig {
135 R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
136 : AMDGPUPassConfig(TM, PM) { }
138 bool addPreISel() override;
139 void addPreRegAlloc() override;
140 void addPreSched2() override;
141 void addPreEmitPass() override;
144 class GCNPassConfig : public AMDGPUPassConfig {
146 GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
147 : AMDGPUPassConfig(TM, PM) { }
148 bool addPreISel() override;
149 bool addInstSelector() override;
150 void addPreRegAlloc() override;
151 void addPostRegAlloc() override;
152 void addPreSched2() override;
153 void addPreEmitPass() override;
156 } // End of anonymous namespace
158 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
159 return TargetIRAnalysis(
160 [this](Function &F) { return TargetTransformInfo(AMDGPUTTIImpl(this)); });
163 void AMDGPUPassConfig::addIRPasses() {
164 // Function calls are not supported, so make sure we inline everything.
165 addPass(createAMDGPUAlwaysInlinePass());
166 addPass(createAlwaysInlinerPass());
167 // We need to add the barrier noop pass, otherwise adding the function
168 // inlining pass will cause all of the PassConfigs passes to be run
169 // one function at a time, which means if we have a nodule with two
170 // functions, then we will generate code for the first function
171 // without ever running any passes on the second.
172 addPass(createBarrierNoopPass());
173 TargetPassConfig::addIRPasses();
176 void AMDGPUPassConfig::addCodeGenPrepare() {
177 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
178 if (ST.isPromoteAllocaEnabled()) {
179 addPass(createAMDGPUPromoteAlloca(ST));
180 addPass(createSROAPass());
182 TargetPassConfig::addCodeGenPrepare();
186 AMDGPUPassConfig::addPreISel() {
187 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
188 addPass(createFlattenCFGPass());
189 if (ST.IsIRStructurizerEnabled())
190 addPass(createStructurizeCFGPass());
194 bool AMDGPUPassConfig::addInstSelector() {
195 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
199 //===----------------------------------------------------------------------===//
201 //===----------------------------------------------------------------------===//
203 bool R600PassConfig::addPreISel() {
204 AMDGPUPassConfig::addPreISel();
205 addPass(createR600TextureIntrinsicsReplacer());
209 void R600PassConfig::addPreRegAlloc() {
210 addPass(createR600VectorRegMerger(*TM));
213 void R600PassConfig::addPreSched2() {
214 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
215 addPass(createR600EmitClauseMarkers(), false);
216 if (ST.isIfCvtEnabled())
217 addPass(&IfConverterID, false);
218 addPass(createR600ClauseMergePass(*TM), false);
221 void R600PassConfig::addPreEmitPass() {
222 addPass(createAMDGPUCFGStructurizerPass(), false);
223 addPass(createR600ExpandSpecialInstrsPass(*TM), false);
224 addPass(&FinalizeMachineBundlesID, false);
225 addPass(createR600Packetizer(*TM), false);
226 addPass(createR600ControlFlowFinalizer(*TM), false);
229 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
230 return new R600PassConfig(this, PM);
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 bool GCNPassConfig::addPreISel() {
238 AMDGPUPassConfig::addPreISel();
239 addPass(createSinkingPass());
240 addPass(createSITypeRewriter());
241 addPass(createSIAnnotateControlFlowPass());
245 bool GCNPassConfig::addInstSelector() {
246 AMDGPUPassConfig::addInstSelector();
247 addPass(createSILowerI1CopiesPass());
248 addPass(createSIFixSGPRCopiesPass(*TM));
249 addPass(createSIFoldOperandsPass());
253 void GCNPassConfig::addPreRegAlloc() {
254 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
255 if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
256 // Don't do this with no optimizations since it throws away debug info by
257 // merging nonadjacent loads.
259 // This should be run after scheduling, but before register allocation. It
260 // also need extra copies to the address operand to be eliminated.
261 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
262 insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
264 addPass(createSIShrinkInstructionsPass(), false);
265 addPass(createSIFixSGPRLiveRangesPass(), false);
268 void GCNPassConfig::addPostRegAlloc() {
269 addPass(createSIPrepareScratchRegs(), false);
270 addPass(createSIShrinkInstructionsPass(), false);
273 void GCNPassConfig::addPreSched2() {
274 addPass(createSIInsertWaits(*TM), false);
277 void GCNPassConfig::addPreEmitPass() {
278 addPass(createSILowerControlFlowPass(*TM), false);
281 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
282 return new GCNPassConfig(this, PM);