1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/IR/Verifier.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/PassManager.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_os_ostream.h"
32 #include "llvm/Transforms/IPO.h"
33 #include "llvm/Transforms/Scalar.h"
34 #include <llvm/CodeGen/Passes.h>
39 extern "C" void LLVMInitializeR600Target() {
40 // Register the target
41 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
44 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
45 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
48 static MachineSchedRegistry
49 SchedCustomRegistry("r600", "Run R600's custom scheduler",
50 createR600MachineScheduler);
52 static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
53 std::string Ret = "e-p:32:32";
56 // 32-bit private, local, and region pointers. 64-bit global and constant.
57 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64";
60 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
61 "-v512:512-v1024:1024-v2048:2048-n32:64";
66 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
67 StringRef CPU, StringRef FS,
68 TargetOptions Options,
69 Reloc::Model RM, CodeModel::Model CM,
70 CodeGenOpt::Level OptLevel
73 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
74 Subtarget(TT, CPU, FS),
75 Layout(computeDataLayout(Subtarget)),
76 FrameLowering(TargetFrameLowering::StackGrowsUp,
77 64 * 16 // Maximum stack alignment (long16)
80 InstrItins(&Subtarget.getInstrItineraryData()) {
81 // TLInfo uses InstrInfo so it must be initialized after.
82 if (Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
83 InstrInfo.reset(new R600InstrInfo(*this));
84 TLInfo.reset(new R600TargetLowering(*this));
86 InstrInfo.reset(new SIInstrInfo(*this));
87 TLInfo.reset(new SITargetLowering(*this));
89 setRequiresStructuredCFG(true);
93 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
97 class AMDGPUPassConfig : public TargetPassConfig {
99 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
100 : TargetPassConfig(TM, PM) {}
102 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
103 return getTM<AMDGPUTargetMachine>();
107 createMachineScheduler(MachineSchedContext *C) const override {
108 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
109 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
110 return createR600MachineScheduler(C);
114 bool addPreISel() override;
115 bool addInstSelector() override;
116 bool addPreRegAlloc() override;
117 bool addPostRegAlloc() override;
118 bool addPreSched2() override;
119 bool addPreEmitPass() override;
121 } // End of anonymous namespace
123 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
124 return new AMDGPUPassConfig(this, PM);
127 //===----------------------------------------------------------------------===//
128 // AMDGPU Analysis Pass Setup
129 //===----------------------------------------------------------------------===//
131 void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
132 // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
133 // allows the AMDGPU pass to delegate to the target independent layer when
135 PM.add(createBasicTargetTransformInfoPass(this));
136 PM.add(createAMDGPUTargetTransformInfoPass(this));
140 AMDGPUPassConfig::addPreISel() {
141 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
142 addPass(createFlattenCFGPass());
143 if (ST.IsIRStructurizerEnabled())
144 addPass(createStructurizeCFGPass());
145 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
146 addPass(createSinkingPass());
147 addPass(createSITypeRewriter());
148 addPass(createSIAnnotateControlFlowPass());
150 addPass(createR600TextureIntrinsicsReplacer());
155 bool AMDGPUPassConfig::addInstSelector() {
156 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
157 addPass(createSILowerI1CopiesPass());
161 bool AMDGPUPassConfig::addPreRegAlloc() {
162 addPass(createAMDGPUConvertToISAPass(*TM));
163 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
165 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
166 addPass(createR600VectorRegMerger(*TM));
168 addPass(createSIFixSGPRCopiesPass(*TM));
169 // SIFixSGPRCopies can generate a lot of duplicate instructions,
170 // so we need to run MachineCSE afterwards.
171 addPass(&MachineCSEID);
176 bool AMDGPUPassConfig::addPostRegAlloc() {
177 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
179 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
180 addPass(createSIInsertWaits(*TM));
185 bool AMDGPUPassConfig::addPreSched2() {
186 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
188 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
189 addPass(createR600EmitClauseMarkers());
190 if (ST.isIfCvtEnabled())
191 addPass(&IfConverterID);
192 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
193 addPass(createR600ClauseMergePass(*TM));
197 bool AMDGPUPassConfig::addPreEmitPass() {
198 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
199 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
200 addPass(createAMDGPUCFGStructurizerPass());
201 addPass(createR600ExpandSpecialInstrsPass(*TM));
202 addPass(&FinalizeMachineBundlesID);
203 addPass(createR600Packetizer(*TM));
204 addPass(createR600ControlFlowFinalizer(*TM));
206 addPass(createSILowerControlFlowPass(*TM));