1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/Analysis/Verifier.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/PassManager.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_os_ostream.h"
32 #include "llvm/Transforms/IPO.h"
33 #include "llvm/Transforms/Scalar.h"
34 #include <llvm/CodeGen/Passes.h>
38 extern "C" void LLVMInitializeR600Target() {
39 // Register the target
40 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
43 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
44 return new ScheduleDAGMI(C, new R600SchedStrategy());
47 static MachineSchedRegistry
48 SchedCustomRegistry("r600", "Run R600's custom scheduler",
49 createR600MachineScheduler);
51 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
52 StringRef CPU, StringRef FS,
53 TargetOptions Options,
54 Reloc::Model RM, CodeModel::Model CM,
55 CodeGenOpt::Level OptLevel
58 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
59 Subtarget(TT, CPU, FS),
60 Layout(Subtarget.getDataLayout()),
61 FrameLowering(TargetFrameLowering::StackGrowsUp,
62 Subtarget.device()->getStackAlignment(), 0),
64 InstrItins(&Subtarget.getInstrItineraryData()) {
65 // TLInfo uses InstrInfo so it must be initialized after.
66 if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
67 InstrInfo.reset(new R600InstrInfo(*this));
68 TLInfo.reset(new R600TargetLowering(*this));
70 InstrInfo.reset(new SIInstrInfo(*this));
71 TLInfo.reset(new SITargetLowering(*this));
76 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
80 class AMDGPUPassConfig : public TargetPassConfig {
82 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
83 : TargetPassConfig(TM, PM) {
84 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
85 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
86 enablePass(&MachineSchedulerID);
87 MachineSchedRegistry::setDefault(createR600MachineScheduler);
91 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
92 return getTM<AMDGPUTargetMachine>();
95 virtual bool addPreISel();
96 virtual bool addInstSelector();
97 virtual bool addPreRegAlloc();
98 virtual bool addPostRegAlloc();
99 virtual bool addPreSched2();
100 virtual bool addPreEmitPass();
102 } // End of anonymous namespace
104 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
105 return new AMDGPUPassConfig(this, PM);
109 AMDGPUPassConfig::addPreISel() {
110 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
111 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
112 addPass(createAMDGPUStructurizeCFGPass());
113 addPass(createSIAnnotateControlFlowPass());
115 addPass(createR600TextureIntrinsicsReplacer());
120 bool AMDGPUPassConfig::addInstSelector() {
121 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
123 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
124 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
125 // This callbacks this pass uses are not implemented yet on SI.
126 addPass(createAMDGPUIndirectAddressingPass(*TM));
131 bool AMDGPUPassConfig::addPreRegAlloc() {
132 addPass(createAMDGPUConvertToISAPass(*TM));
136 bool AMDGPUPassConfig::addPostRegAlloc() {
137 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
139 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
140 addPass(createSIInsertWaits(*TM));
145 bool AMDGPUPassConfig::addPreSched2() {
147 addPass(&IfConverterID);
151 bool AMDGPUPassConfig::addPreEmitPass() {
152 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
153 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
154 addPass(createAMDGPUCFGPreparationPass(*TM));
155 addPass(createAMDGPUCFGStructurizerPass(*TM));
156 addPass(createR600EmitClauseMarkers(*TM));
157 addPass(createR600ExpandSpecialInstrsPass(*TM));
158 addPass(&FinalizeMachineBundlesID);
159 addPass(createR600Packetizer(*TM));
160 addPass(createR600ControlFlowFinalizer(*TM));
162 addPass(createSILowerControlFlowPass(*TM));