1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Verifier.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/PassManager.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_os_ostream.h"
33 #include "llvm/Transforms/IPO.h"
34 #include "llvm/Transforms/Scalar.h"
35 #include <llvm/CodeGen/Passes.h>
39 extern "C" void LLVMInitializeR600Target() {
40 // Register the target
41 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
42 RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
45 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
46 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
49 static MachineSchedRegistry
50 SchedCustomRegistry("r600", "Run R600's custom scheduler",
51 createR600MachineScheduler);
53 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
54 StringRef CPU, StringRef FS,
55 TargetOptions Options, Reloc::Model RM,
57 CodeGenOpt::Level OptLevel)
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
59 TLOF(new TargetLoweringObjectFileELF()),
60 Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
61 setRequiresStructuredCFG(true);
65 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
70 class AMDGPUPassConfig : public TargetPassConfig {
72 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
73 : TargetPassConfig(TM, PM) {}
75 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
76 return getTM<AMDGPUTargetMachine>();
80 createMachineScheduler(MachineSchedContext *C) const override {
81 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
82 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
83 return createR600MachineScheduler(C);
87 void addIRPasses() override;
88 void addCodeGenPrepare() override;
89 bool addPreISel() override;
90 bool addInstSelector() override;
91 void addPreRegAlloc() override;
92 void addPostRegAlloc() override;
93 void addPreSched2() override;
94 void addPreEmitPass() override;
96 } // End of anonymous namespace
98 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
99 return new AMDGPUPassConfig(this, PM);
102 //===----------------------------------------------------------------------===//
103 // AMDGPU Analysis Pass Setup
104 //===----------------------------------------------------------------------===//
106 void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
107 // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
108 // allows the AMDGPU pass to delegate to the target independent layer when
110 PM.add(createBasicTargetTransformInfoPass(this));
111 PM.add(createAMDGPUTargetTransformInfoPass(this));
114 void AMDGPUPassConfig::addIRPasses() {
115 // Function calls are not supported, so make sure we inline everything.
116 addPass(createAMDGPUAlwaysInlinePass());
117 addPass(createAlwaysInlinerPass());
118 // We need to add the barrier noop pass, otherwise adding the function
119 // inlining pass will cause all of the PassConfigs passes to be run
120 // one function at a time, which means if we have a nodule with two
121 // functions, then we will generate code for the first function
122 // without ever running any passes on the second.
123 addPass(createBarrierNoopPass());
124 TargetPassConfig::addIRPasses();
127 void AMDGPUPassConfig::addCodeGenPrepare() {
128 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
129 if (ST.isPromoteAllocaEnabled()) {
130 addPass(createAMDGPUPromoteAlloca(ST));
131 addPass(createSROAPass());
134 TargetPassConfig::addCodeGenPrepare();
138 AMDGPUPassConfig::addPreISel() {
139 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
140 addPass(createFlattenCFGPass());
141 if (ST.IsIRStructurizerEnabled())
142 addPass(createStructurizeCFGPass());
143 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
144 addPass(createSinkingPass());
145 addPass(createSITypeRewriter());
146 addPass(createSIAnnotateControlFlowPass());
148 addPass(createR600TextureIntrinsicsReplacer());
153 bool AMDGPUPassConfig::addInstSelector() {
154 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
156 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
158 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
159 addPass(createSILowerI1CopiesPass());
160 addPass(createSIFixSGPRCopiesPass(*TM));
161 addPass(createSIFoldOperandsPass());
167 void AMDGPUPassConfig::addPreRegAlloc() {
168 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
170 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
171 addPass(createR600VectorRegMerger(*TM));
173 if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
174 // Don't do this with no optimizations since it throws away debug info by
175 // merging nonadjacent loads.
177 // This should be run after scheduling, but before register allocation. It
178 // also need extra copies to the address operand to be eliminated.
179 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
180 insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
183 addPass(createSIShrinkInstructionsPass(), false);
184 addPass(createSIFixSGPRLiveRangesPass(), false);
188 void AMDGPUPassConfig::addPostRegAlloc() {
189 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
191 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
192 addPass(createSIPrepareScratchRegs(), false);
193 addPass(createSIShrinkInstructionsPass(), false);
197 void AMDGPUPassConfig::addPreSched2() {
198 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
200 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
201 addPass(createR600EmitClauseMarkers(), false);
202 if (ST.isIfCvtEnabled())
203 addPass(&IfConverterID, false);
204 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
205 addPass(createR600ClauseMergePass(*TM), false);
206 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
207 addPass(createSIInsertWaits(*TM), false);
211 void AMDGPUPassConfig::addPreEmitPass() {
212 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
213 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
214 addPass(createAMDGPUCFGStructurizerPass(), false);
215 addPass(createR600ExpandSpecialInstrsPass(*TM), false);
216 addPass(&FinalizeMachineBundlesID, false);
217 addPass(createR600Packetizer(*TM), false);
218 addPass(createR600ControlFlowFinalizer(*TM), false);
220 addPass(createSILowerControlFlowPass(*TM), false);
225 //===----------------------------------------------------------------------===//
226 // GCN Target Machine (SI+)
227 //===----------------------------------------------------------------------===//
229 GCNTargetMachine::GCNTargetMachine(const Target &T, StringRef TT, StringRef FS,
230 StringRef CPU, TargetOptions Options, Reloc::Model RM,
231 CodeModel::Model CM, CodeGenOpt::Level OL) :
232 AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) { }