1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Verifier.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/PassManager.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_os_ostream.h"
33 #include "llvm/Transforms/IPO.h"
34 #include "llvm/Transforms/Scalar.h"
35 #include <llvm/CodeGen/Passes.h>
39 extern "C" void LLVMInitializeR600Target() {
40 // Register the target
41 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
42 RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
45 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
46 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
49 static MachineSchedRegistry
50 SchedCustomRegistry("r600", "Run R600's custom scheduler",
51 createR600MachineScheduler);
53 static std::string computeDataLayout(StringRef TT) {
55 std::string Ret = "e-p:32:32";
57 if (Triple.getArch() == Triple::amdgcn) {
58 // 32-bit private, local, and region pointers. 64-bit global and constant.
59 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
62 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
63 "-v512:512-v1024:1024-v2048:2048-n32:64";
68 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
69 StringRef CPU, StringRef FS,
70 TargetOptions Options, Reloc::Model RM,
72 CodeGenOpt::Level OptLevel)
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
74 DL(computeDataLayout(TT)),
75 TLOF(new TargetLoweringObjectFileELF()),
76 Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
77 setRequiresStructuredCFG(true);
81 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
86 class AMDGPUPassConfig : public TargetPassConfig {
88 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
89 : TargetPassConfig(TM, PM) {}
91 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
92 return getTM<AMDGPUTargetMachine>();
96 createMachineScheduler(MachineSchedContext *C) const override {
97 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
98 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
99 return createR600MachineScheduler(C);
103 void addIRPasses() override;
104 void addCodeGenPrepare() override;
105 bool addPreISel() override;
106 bool addInstSelector() override;
107 void addPreRegAlloc() override;
108 void addPostRegAlloc() override;
109 void addPreSched2() override;
110 void addPreEmitPass() override;
112 } // End of anonymous namespace
114 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
115 return new AMDGPUPassConfig(this, PM);
118 //===----------------------------------------------------------------------===//
119 // AMDGPU Analysis Pass Setup
120 //===----------------------------------------------------------------------===//
122 void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
123 // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
124 // allows the AMDGPU pass to delegate to the target independent layer when
126 PM.add(createBasicTargetTransformInfoPass(this));
127 PM.add(createAMDGPUTargetTransformInfoPass(this));
130 void AMDGPUPassConfig::addIRPasses() {
131 // Function calls are not supported, so make sure we inline everything.
132 addPass(createAMDGPUAlwaysInlinePass());
133 addPass(createAlwaysInlinerPass());
134 // We need to add the barrier noop pass, otherwise adding the function
135 // inlining pass will cause all of the PassConfigs passes to be run
136 // one function at a time, which means if we have a nodule with two
137 // functions, then we will generate code for the first function
138 // without ever running any passes on the second.
139 addPass(createBarrierNoopPass());
140 TargetPassConfig::addIRPasses();
143 void AMDGPUPassConfig::addCodeGenPrepare() {
144 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
145 if (ST.isPromoteAllocaEnabled()) {
146 addPass(createAMDGPUPromoteAlloca(ST));
147 addPass(createSROAPass());
150 TargetPassConfig::addCodeGenPrepare();
154 AMDGPUPassConfig::addPreISel() {
155 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
156 addPass(createFlattenCFGPass());
157 if (ST.IsIRStructurizerEnabled())
158 addPass(createStructurizeCFGPass());
159 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
160 addPass(createSinkingPass());
161 addPass(createSITypeRewriter());
162 addPass(createSIAnnotateControlFlowPass());
164 addPass(createR600TextureIntrinsicsReplacer());
169 bool AMDGPUPassConfig::addInstSelector() {
170 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
172 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
174 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
175 addPass(createSILowerI1CopiesPass());
176 addPass(createSIFixSGPRCopiesPass(*TM));
177 addPass(createSIFoldOperandsPass());
183 void AMDGPUPassConfig::addPreRegAlloc() {
184 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
186 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
187 addPass(createR600VectorRegMerger(*TM));
189 if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
190 // Don't do this with no optimizations since it throws away debug info by
191 // merging nonadjacent loads.
193 // This should be run after scheduling, but before register allocation. It
194 // also need extra copies to the address operand to be eliminated.
195 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
196 insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
199 addPass(createSIShrinkInstructionsPass(), false);
200 addPass(createSIFixSGPRLiveRangesPass(), false);
204 void AMDGPUPassConfig::addPostRegAlloc() {
205 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
207 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
208 addPass(createSIPrepareScratchRegs(), false);
209 addPass(createSIShrinkInstructionsPass(), false);
213 void AMDGPUPassConfig::addPreSched2() {
214 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
216 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
217 addPass(createR600EmitClauseMarkers(), false);
218 if (ST.isIfCvtEnabled())
219 addPass(&IfConverterID, false);
220 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
221 addPass(createR600ClauseMergePass(*TM), false);
222 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
223 addPass(createSIInsertWaits(*TM), false);
227 void AMDGPUPassConfig::addPreEmitPass() {
228 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
229 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
230 addPass(createAMDGPUCFGStructurizerPass(), false);
231 addPass(createR600ExpandSpecialInstrsPass(*TM), false);
232 addPass(&FinalizeMachineBundlesID, false);
233 addPass(createR600Packetizer(*TM), false);
234 addPass(createR600ControlFlowFinalizer(*TM), false);
236 addPass(createSILowerControlFlowPass(*TM), false);
241 //===----------------------------------------------------------------------===//
242 // GCN Target Machine (SI+)
243 //===----------------------------------------------------------------------===//
245 GCNTargetMachine::GCNTargetMachine(const Target &T, StringRef TT, StringRef FS,
246 StringRef CPU, TargetOptions Options, Reloc::Model RM,
247 CodeModel::Model CM, CodeGenOpt::Level OL) :
248 AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) { }