1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/Analysis/Verifier.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/PassManager.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_os_ostream.h"
32 #include "llvm/Transforms/IPO.h"
33 #include "llvm/Transforms/Scalar.h"
34 #include <llvm/CodeGen/Passes.h>
39 extern "C" void LLVMInitializeR600Target() {
40 // Register the target
41 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
44 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
45 return new ScheduleDAGMI(C, new R600SchedStrategy());
48 static MachineSchedRegistry
49 SchedCustomRegistry("r600", "Run R600's custom scheduler",
50 createR600MachineScheduler);
52 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
53 StringRef CPU, StringRef FS,
54 TargetOptions Options,
55 Reloc::Model RM, CodeModel::Model CM,
56 CodeGenOpt::Level OptLevel
59 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
60 Subtarget(TT, CPU, FS),
61 Layout(Subtarget.getDataLayout()),
62 FrameLowering(TargetFrameLowering::StackGrowsUp,
63 64 * 16 // Maximum stack alignment (long16)
66 InstrItins(&Subtarget.getInstrItineraryData()) {
67 // TLInfo uses InstrInfo so it must be initialized after.
68 if (Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
69 InstrInfo.reset(new R600InstrInfo(*this));
70 TLInfo.reset(new R600TargetLowering(*this));
72 InstrInfo.reset(new SIInstrInfo(*this));
73 TLInfo.reset(new SITargetLowering(*this));
78 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
82 class AMDGPUPassConfig : public TargetPassConfig {
84 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
85 : TargetPassConfig(TM, PM) {}
87 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
88 return getTM<AMDGPUTargetMachine>();
91 virtual ScheduleDAGInstrs *
92 createMachineScheduler(MachineSchedContext *C) const {
93 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
94 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
95 return createR600MachineScheduler(C);
99 virtual bool addPreISel();
100 virtual bool addInstSelector();
101 virtual bool addPreRegAlloc();
102 virtual bool addPostRegAlloc();
103 virtual bool addPreSched2();
104 virtual bool addPreEmitPass();
106 } // End of anonymous namespace
108 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
109 return new AMDGPUPassConfig(this, PM);
112 //===----------------------------------------------------------------------===//
113 // AMDGPU Analysis Pass Setup
114 //===----------------------------------------------------------------------===//
116 void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
117 // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
118 // allows the AMDGPU pass to delegate to the target independent layer when
120 PM.add(createBasicTargetTransformInfoPass(this));
121 PM.add(createAMDGPUTargetTransformInfoPass(this));
125 AMDGPUPassConfig::addPreISel() {
126 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
127 addPass(createFlattenCFGPass());
128 if (ST.IsIRStructurizerEnabled() ||
129 ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS)
130 addPass(createStructurizeCFGPass());
131 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
132 addPass(createSinkingPass());
133 addPass(createSITypeRewriter());
134 addPass(createSIAnnotateControlFlowPass());
136 addPass(createR600TextureIntrinsicsReplacer());
141 bool AMDGPUPassConfig::addInstSelector() {
142 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
146 bool AMDGPUPassConfig::addPreRegAlloc() {
147 addPass(createAMDGPUConvertToISAPass(*TM));
148 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
150 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
151 addPass(createR600VectorRegMerger(*TM));
153 addPass(createSIFixSGPRCopiesPass(*TM));
158 bool AMDGPUPassConfig::addPostRegAlloc() {
159 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
161 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
162 addPass(createSIInsertWaits(*TM));
167 bool AMDGPUPassConfig::addPreSched2() {
168 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
170 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
171 addPass(createR600EmitClauseMarkers(*TM));
172 addPass(&IfConverterID);
173 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
174 addPass(createR600ClauseMergePass(*TM));
178 bool AMDGPUPassConfig::addPreEmitPass() {
179 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
180 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
181 addPass(createAMDGPUCFGStructurizerPass(*TM));
182 addPass(createR600ExpandSpecialInstrsPass(*TM));
183 addPass(&FinalizeMachineBundlesID);
184 addPass(createR600Packetizer(*TM));
185 addPass(createR600ControlFlowFinalizer(*TM));
187 addPass(createSILowerControlFlowPass(*TM));