1 //===-- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // This file implements a TargetTransformInfo analysis pass specific to the
12 // AMDGPU target machine. It uses the target's detailed information to provide
13 // more precise answers to certain TTI queries, while letting the target
14 // independent and default TTI implementations handle the rest.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUTargetMachine.h"
20 #include "llvm/Analysis/LoopInfo.h"
21 #include "llvm/Analysis/TargetTransformInfo.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/BasicTTIImpl.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Target/CostTable.h"
26 #include "llvm/Target/TargetLowering.h"
29 #define DEBUG_TYPE "AMDGPUtti"
33 class AMDGPUTTIImpl : public BasicTTIImplBase<AMDGPUTTIImpl> {
34 typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
35 typedef TargetTransformInfo TTI;
37 const AMDGPUSubtarget *ST;
40 explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM = nullptr)
41 : BaseT(TM), ST(TM->getSubtargetImpl()) {}
43 // Provide value semantics. MSVC requires that we spell all of these out.
44 AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg)
45 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST) {}
46 AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg)
47 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)) {}
48 AMDGPUTTIImpl &operator=(const AMDGPUTTIImpl &RHS) {
49 BaseT::operator=(static_cast<const BaseT &>(RHS));
53 AMDGPUTTIImpl &operator=(AMDGPUTTIImpl &&RHS) {
54 BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
55 ST = std::move(RHS.ST);
59 bool hasBranchDivergence() { return true; }
61 void getUnrollingPreferences(const Function *F, Loop *L,
62 TTI::UnrollingPreferences &UP);
64 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
65 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
66 return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;
69 unsigned getNumberOfRegisters(bool Vector);
70 unsigned getRegisterBitWidth(bool Vector);
71 unsigned getMaxInterleaveFactor();
74 } // end anonymous namespace
77 llvm::createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM) {
78 return new TargetTransformInfoWrapperPass(AMDGPUTTIImpl(TM));
81 void AMDGPUTTIImpl::getUnrollingPreferences(const Function *, Loop *L,
82 TTI::UnrollingPreferences &UP) {
83 UP.Threshold = 300; // Twice the default.
87 // TODO: Do we want runtime unrolling?
89 for (const BasicBlock *BB : L->getBlocks()) {
90 for (const Instruction &I : *BB) {
91 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I);
92 if (!GEP || GEP->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
95 const Value *Ptr = GEP->getPointerOperand();
96 const AllocaInst *Alloca = dyn_cast<AllocaInst>(GetUnderlyingObject(Ptr));
98 // We want to do whatever we can to limit the number of alloca
99 // instructions that make it through to the code generator. allocas
100 // require us to use indirect addressing, which is slow and prone to
101 // compiler bugs. If this loop does an address calculation on an
102 // alloca ptr, then we want to use a higher than normal loop unroll
103 // threshold. This will give SROA a better chance to eliminate these
106 // Don't use the maximum allowed value here as it will make some
107 // programs way too big.
114 unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {
118 // Number of VGPRs on SI.
119 if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
122 return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
125 unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool) { return 32; }
127 unsigned AMDGPUTTIImpl::getMaxInterleaveFactor() {
128 // Semi-arbitrary large amount.