1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDILDevices.h"
18 #include "R600InstrInfo.h"
19 #include "llvm/ADT/ValueMap.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/Support/Compiler.h"
28 //===----------------------------------------------------------------------===//
29 // Instruction Selector Implementation
30 //===----------------------------------------------------------------------===//
33 /// AMDGPU specific code to select AMDGPU machine instructions for
34 /// SelectionDAG operations.
35 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
36 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
37 // make the right decision when generating code for different targets.
38 const AMDGPUSubtarget &Subtarget;
40 AMDGPUDAGToDAGISel(TargetMachine &TM);
41 virtual ~AMDGPUDAGToDAGISel();
43 SDNode *Select(SDNode *N);
44 virtual const char *getPassName() const;
47 inline SDValue getSmallIPtrImm(unsigned Imm);
49 // Complex pattern selectors
50 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
51 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
52 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
54 static bool checkType(const Value *ptr, unsigned int addrspace);
55 static const Value *getBasePointerValue(const Value *V);
57 static bool isGlobalStore(const StoreSDNode *N);
58 static bool isPrivateStore(const StoreSDNode *N);
59 static bool isLocalStore(const StoreSDNode *N);
60 static bool isRegionStore(const StoreSDNode *N);
62 static bool isCPLoad(const LoadSDNode *N);
63 static bool isConstantLoad(const LoadSDNode *N, int cbID);
64 static bool isGlobalLoad(const LoadSDNode *N);
65 static bool isParamLoad(const LoadSDNode *N);
66 static bool isPrivateLoad(const LoadSDNode *N);
67 static bool isLocalLoad(const LoadSDNode *N);
68 static bool isRegionLoad(const LoadSDNode *N);
70 bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset);
71 bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
72 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
74 // Include the pieces autogenerated from the target description.
75 #include "AMDGPUGenDAGISel.inc"
77 } // end anonymous namespace
79 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
80 // DAG, ready for instruction scheduling.
81 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
83 return new AMDGPUDAGToDAGISel(TM);
86 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
88 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
91 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
94 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i32);
98 bool AMDGPUDAGToDAGISel::SelectADDRParam(
99 SDValue Addr, SDValue& R1, SDValue& R2) {
101 if (Addr.getOpcode() == ISD::FrameIndex) {
102 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
103 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
104 R2 = CurDAG->getTargetConstant(0, MVT::i32);
107 R2 = CurDAG->getTargetConstant(0, MVT::i32);
109 } else if (Addr.getOpcode() == ISD::ADD) {
110 R1 = Addr.getOperand(0);
111 R2 = Addr.getOperand(1);
114 R2 = CurDAG->getTargetConstant(0, MVT::i32);
119 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
120 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
121 Addr.getOpcode() == ISD::TargetGlobalAddress) {
124 return SelectADDRParam(Addr, R1, R2);
128 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
129 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
130 Addr.getOpcode() == ISD::TargetGlobalAddress) {
134 if (Addr.getOpcode() == ISD::FrameIndex) {
135 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
136 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
137 R2 = CurDAG->getTargetConstant(0, MVT::i64);
140 R2 = CurDAG->getTargetConstant(0, MVT::i64);
142 } else if (Addr.getOpcode() == ISD::ADD) {
143 R1 = Addr.getOperand(0);
144 R2 = Addr.getOperand(1);
147 R2 = CurDAG->getTargetConstant(0, MVT::i64);
152 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
153 unsigned int Opc = N->getOpcode();
154 if (N->isMachineOpcode()) {
155 return NULL; // Already selected.
159 case ISD::FrameIndex: {
160 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
161 unsigned int FI = FIN->getIndex();
162 EVT OpVT = N->getValueType(0);
163 unsigned int NewOpc = AMDGPU::COPY;
164 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
165 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
169 case ISD::ConstantFP:
170 case ISD::Constant: {
171 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
172 // XXX: Custom immediate lowering not implemented yet. Instead we use
173 // pseudo instructions defined in SIInstructions.td
174 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
177 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
179 uint64_t ImmValue = 0;
180 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
182 if (N->getOpcode() == ISD::ConstantFP) {
183 // XXX: 64-bit Immediates not supported yet
184 assert(N->getValueType(0) != MVT::f64);
186 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
187 APFloat Value = C->getValueAPF();
188 float FloatValue = Value.convertToFloat();
189 if (FloatValue == 0.0) {
190 ImmReg = AMDGPU::ZERO;
191 } else if (FloatValue == 0.5) {
192 ImmReg = AMDGPU::HALF;
193 } else if (FloatValue == 1.0) {
194 ImmReg = AMDGPU::ONE;
196 ImmValue = Value.bitcastToAPInt().getZExtValue();
199 // XXX: 64-bit Immediates not supported yet
200 assert(N->getValueType(0) != MVT::i64);
202 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
203 if (C->getZExtValue() == 0) {
204 ImmReg = AMDGPU::ZERO;
205 } else if (C->getZExtValue() == 1) {
206 ImmReg = AMDGPU::ONE_INT;
208 ImmValue = C->getZExtValue();
212 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
213 Use != SDNode::use_end(); Use = Next) {
214 Next = llvm::next(Use);
215 std::vector<SDValue> Ops;
216 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
217 Ops.push_back(Use->getOperand(i));
220 if (!Use->isMachineOpcode()) {
221 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
222 // We can only use literal constants (e.g. AMDGPU::ZERO,
223 // AMDGPU::ONE, etc) in machine opcodes.
227 if (!TII->isALUInstr(Use->getMachineOpcode())) {
231 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
232 assert(ImmIdx != -1);
234 // subtract one from ImmIdx, because the DST operand is usually index
235 // 0 for MachineInstrs, but we have no DST in the Ops vector.
238 // Check that we aren't already using an immediate.
239 // XXX: It's possible for an instruction to have more than one
240 // immediate operand, but this is not supported yet.
241 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
242 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
245 if (C->getZExtValue() != 0) {
246 // This instruction is already using an immediate.
250 // Set the immediate value
251 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
254 // Set the immediate register
255 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
257 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
262 return SelectCode(N);
265 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
269 Type *ptrType = ptr->getType();
270 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
273 const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
277 const Value *ret = NULL;
278 ValueMap<const Value *, bool> ValueBitMap;
279 std::queue<const Value *, std::list<const Value *> > ValueQueue;
281 while (!ValueQueue.empty()) {
282 V = ValueQueue.front();
283 if (ValueBitMap.find(V) == ValueBitMap.end()) {
284 ValueBitMap[V] = true;
285 if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
288 } else if (dyn_cast<GlobalVariable>(V)) {
291 } else if (dyn_cast<Constant>(V)) {
292 const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
294 ValueQueue.push(CE->getOperand(0));
296 } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
299 } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
300 uint32_t numOps = I->getNumOperands();
301 for (uint32_t x = 0; x < numOps; ++x) {
302 ValueQueue.push(I->getOperand(x));
305 assert(!"Found a Value that we didn't know how to handle!");
313 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
314 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
317 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
318 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
319 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
320 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
323 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
324 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
327 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
328 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
331 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
332 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
335 MachineMemOperand *MMO = N->getMemOperand();
336 const Value *V = MMO->getValue();
337 const Value *BV = getBasePointerValue(V);
340 && ((V && dyn_cast<GlobalValue>(V))
341 || (BV && dyn_cast<GlobalValue>(
342 getBasePointerValue(MMO->getValue()))))) {
343 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
349 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
350 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
353 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
354 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
357 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
358 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
361 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
362 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
365 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
366 MachineMemOperand *MMO = N->getMemOperand();
367 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
369 const Value *V = MMO->getValue();
370 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
371 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
379 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
380 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
381 // Check to make sure we are not a constant pool load or a constant load
382 // that is marked as a private load
383 if (isCPLoad(N) || isConstantLoad(N, -1)) {
387 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
388 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
389 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
390 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
391 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
392 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
398 const char *AMDGPUDAGToDAGISel::getPassName() const {
399 return "AMDGPU DAG->DAG Pattern Instruction Selection";
407 ///==== AMDGPU Functions ====///
409 bool AMDGPUDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
411 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
412 Addr.getOpcode() == ISD::TargetGlobalAddress) {
417 if (Addr.getOpcode() == ISD::ADD) {
420 // Find the base ptr and the offset
421 for (unsigned i = 0; i < Addr.getNumOperands(); i++) {
422 SDValue Arg = Addr.getOperand(i);
423 ConstantSDNode * OffsetNode = dyn_cast<ConstantSDNode>(Arg);
424 // This arg isn't a constant so it must be the base PTR.
426 Base = Addr.getOperand(i);
429 // Check if the constant argument fits in 8-bits. The offset is in bytes
430 // so we need to convert it to dwords.
431 if (isUInt<8>(OffsetNode->getZExtValue() >> 2)) {
433 Offset = CurDAG->getTargetConstant(OffsetNode->getZExtValue() >> 2,
440 // Default case, no offset
442 Offset = CurDAG->getTargetConstant(0, MVT::i32);
446 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
448 ConstantSDNode * IMMOffset;
450 if (Addr.getOpcode() == ISD::ADD
451 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
452 && isInt<16>(IMMOffset->getZExtValue())) {
454 Base = Addr.getOperand(0);
455 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
457 // If the pointer address is constant, we can move it to the offset field.
458 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
459 && isInt<16>(IMMOffset->getZExtValue())) {
460 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
461 CurDAG->getEntryNode().getDebugLoc(),
462 AMDGPU::ZERO, MVT::i32);
463 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
467 // Default case, no offset
469 Offset = CurDAG->getTargetConstant(0, MVT::i32);
473 bool AMDGPUDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
475 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
476 Addr.getOpcode() == ISD::TargetGlobalAddress ||
477 Addr.getOpcode() != ISD::ADD) {
481 Base = Addr.getOperand(0);
482 Offset = Addr.getOperand(1);