1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "R600InstrInfo.h"
18 #include "SIISelLowering.h"
19 #include "llvm/ADT/ValueMap.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Support/Compiler.h"
31 //===----------------------------------------------------------------------===//
32 // Instruction Selector Implementation
33 //===----------------------------------------------------------------------===//
36 /// AMDGPU specific code to select AMDGPU machine instructions for
37 /// SelectionDAG operations.
38 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
39 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
40 // make the right decision when generating code for different targets.
41 const AMDGPUSubtarget &Subtarget;
43 AMDGPUDAGToDAGISel(TargetMachine &TM);
44 virtual ~AMDGPUDAGToDAGISel();
46 SDNode *Select(SDNode *N);
47 virtual const char *getPassName() const;
48 virtual void PostprocessISelDAG();
51 inline SDValue getSmallIPtrImm(unsigned Imm);
52 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
53 const R600InstrInfo *TII, std::vector<unsigned> Cst);
54 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
55 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 // Complex pattern selectors
58 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
59 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
60 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
62 static bool checkType(const Value *ptr, unsigned int addrspace);
64 static bool isGlobalStore(const StoreSDNode *N);
65 static bool isPrivateStore(const StoreSDNode *N);
66 static bool isLocalStore(const StoreSDNode *N);
67 static bool isRegionStore(const StoreSDNode *N);
69 bool isCPLoad(const LoadSDNode *N) const;
70 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
71 bool isGlobalLoad(const LoadSDNode *N) const;
72 bool isParamLoad(const LoadSDNode *N) const;
73 bool isPrivateLoad(const LoadSDNode *N) const;
74 bool isLocalLoad(const LoadSDNode *N) const;
75 bool isRegionLoad(const LoadSDNode *N) const;
77 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
78 bool SelectGlobalValueVariableOffset(SDValue Addr,
79 SDValue &BaseReg, SDValue& Offset);
80 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
81 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
83 // Include the pieces autogenerated from the target description.
84 #include "AMDGPUGenDAGISel.inc"
86 } // end anonymous namespace
88 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
89 // DAG, ready for instruction scheduling.
90 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
92 return new AMDGPUDAGToDAGISel(TM);
95 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
97 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
100 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
103 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
104 return CurDAG->getTargetConstant(Imm, MVT::i32);
107 bool AMDGPUDAGToDAGISel::SelectADDRParam(
108 SDValue Addr, SDValue& R1, SDValue& R2) {
110 if (Addr.getOpcode() == ISD::FrameIndex) {
111 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
112 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
113 R2 = CurDAG->getTargetConstant(0, MVT::i32);
116 R2 = CurDAG->getTargetConstant(0, MVT::i32);
118 } else if (Addr.getOpcode() == ISD::ADD) {
119 R1 = Addr.getOperand(0);
120 R2 = Addr.getOperand(1);
123 R2 = CurDAG->getTargetConstant(0, MVT::i32);
128 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
129 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
130 Addr.getOpcode() == ISD::TargetGlobalAddress) {
133 return SelectADDRParam(Addr, R1, R2);
137 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
138 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
139 Addr.getOpcode() == ISD::TargetGlobalAddress) {
143 if (Addr.getOpcode() == ISD::FrameIndex) {
144 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
145 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
146 R2 = CurDAG->getTargetConstant(0, MVT::i64);
149 R2 = CurDAG->getTargetConstant(0, MVT::i64);
151 } else if (Addr.getOpcode() == ISD::ADD) {
152 R1 = Addr.getOperand(0);
153 R2 = Addr.getOperand(1);
156 R2 = CurDAG->getTargetConstant(0, MVT::i64);
161 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
162 unsigned int Opc = N->getOpcode();
163 if (N->isMachineOpcode()) {
164 return NULL; // Already selected.
168 case ISD::BUILD_VECTOR: {
169 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
170 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
173 // BUILD_VECTOR is usually lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
174 // that adds a 128 bits reg copy when going through TwoAddressInstructions
175 // pass. We want to avoid 128 bits copies as much as possible because they
176 // can't be bundled by our scheduler.
177 SDValue RegSeqArgs[9] = {
178 CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32),
179 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
180 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
181 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
182 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
184 bool IsRegSeq = true;
185 for (unsigned i = 0; i < N->getNumOperands(); i++) {
186 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
190 RegSeqArgs[2 * i + 1] = N->getOperand(i);
194 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
195 RegSeqArgs, 2 * N->getNumOperands() + 1);
197 case ISD::BUILD_PAIR: {
198 SDValue RC, SubReg0, SubReg1;
199 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
200 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
203 if (N->getValueType(0) == MVT::i128) {
204 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
205 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
206 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
207 } else if (N->getValueType(0) == MVT::i64) {
208 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
209 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
210 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
212 llvm_unreachable("Unhandled value type for BUILD_PAIR");
214 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
215 N->getOperand(1), SubReg1 };
216 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
217 SDLoc(N), N->getValueType(0), Ops);
220 case ISD::ConstantFP:
221 case ISD::Constant: {
222 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
223 // XXX: Custom immediate lowering not implemented yet. Instead we use
224 // pseudo instructions defined in SIInstructions.td
225 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
228 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
230 uint64_t ImmValue = 0;
231 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
233 if (N->getOpcode() == ISD::ConstantFP) {
234 // XXX: 64-bit Immediates not supported yet
235 assert(N->getValueType(0) != MVT::f64);
237 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
238 APFloat Value = C->getValueAPF();
239 float FloatValue = Value.convertToFloat();
240 if (FloatValue == 0.0) {
241 ImmReg = AMDGPU::ZERO;
242 } else if (FloatValue == 0.5) {
243 ImmReg = AMDGPU::HALF;
244 } else if (FloatValue == 1.0) {
245 ImmReg = AMDGPU::ONE;
247 ImmValue = Value.bitcastToAPInt().getZExtValue();
250 // XXX: 64-bit Immediates not supported yet
251 assert(N->getValueType(0) != MVT::i64);
253 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
254 if (C->getZExtValue() == 0) {
255 ImmReg = AMDGPU::ZERO;
256 } else if (C->getZExtValue() == 1) {
257 ImmReg = AMDGPU::ONE_INT;
259 ImmValue = C->getZExtValue();
263 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
264 Use != SDNode::use_end(); Use = Next) {
265 Next = llvm::next(Use);
266 std::vector<SDValue> Ops;
267 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
268 Ops.push_back(Use->getOperand(i));
271 if (!Use->isMachineOpcode()) {
272 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
273 // We can only use literal constants (e.g. AMDGPU::ZERO,
274 // AMDGPU::ONE, etc) in machine opcodes.
278 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
279 (TII->get(Use->getMachineOpcode()).TSFlags &
280 R600_InstFlag::VECTOR)) {
284 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
285 assert(ImmIdx != -1);
287 // subtract one from ImmIdx, because the DST operand is usually index
288 // 0 for MachineInstrs, but we have no DST in the Ops vector.
291 // Check that we aren't already using an immediate.
292 // XXX: It's possible for an instruction to have more than one
293 // immediate operand, but this is not supported yet.
294 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
295 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
298 if (C->getZExtValue() != 0) {
299 // This instruction is already using an immediate.
303 // Set the immediate value
304 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
307 // Set the immediate register
308 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
310 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
315 SDNode *Result = SelectCode(N);
317 // Fold operands of selected node
319 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
320 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
321 const R600InstrInfo *TII =
322 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
323 if (Result && Result->isMachineOpcode() && Result->getMachineOpcode() == AMDGPU::DOT_4) {
324 bool IsModified = false;
326 std::vector<SDValue> Ops;
327 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
330 IsModified = FoldDotOperands(Result->getMachineOpcode(), TII, Ops);
332 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
334 } while (IsModified);
337 if (Result && Result->isMachineOpcode() &&
338 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
339 && TII->isALUInstr(Result->getMachineOpcode())) {
340 // Fold FNEG/FABS/CONST_ADDRESS
341 // TODO: Isel can generate multiple MachineInst, we need to recursively
343 bool IsModified = false;
345 std::vector<SDValue> Ops;
346 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
349 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
351 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
353 } while (IsModified);
355 // If node has a single use which is CLAMP_R600, folds it
356 if (Result->hasOneUse() && Result->isMachineOpcode()) {
357 SDNode *PotentialClamp = *Result->use_begin();
358 if (PotentialClamp->isMachineOpcode() &&
359 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
361 TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
362 std::vector<SDValue> Ops;
363 unsigned NumOp = Result->getNumOperands();
364 for (unsigned i = 0; i < NumOp; ++i) {
365 Ops.push_back(Result->getOperand(i));
367 Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
368 Result = CurDAG->SelectNodeTo(PotentialClamp,
369 Result->getMachineOpcode(), PotentialClamp->getVTList(),
379 bool AMDGPUDAGToDAGISel::FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg,
380 SDValue &Abs, const R600InstrInfo *TII,
381 std::vector<unsigned> Consts) {
382 switch (Src.getOpcode()) {
383 case AMDGPUISD::CONST_ADDRESS: {
385 if (Src.getValueType().isVector() ||
386 !SelectGlobalValueConstantOffset(Src.getOperand(0), CstOffset))
389 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
390 Consts.push_back(Cst->getZExtValue());
391 if (!TII->fitsConstReadLimitations(Consts))
394 Src = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
399 Src = Src.getOperand(0);
400 Neg = CurDAG->getTargetConstant(1, MVT::i32);
405 Src = Src.getOperand(0);
406 Abs = CurDAG->getTargetConstant(1, MVT::i32);
409 Src = Src.getOperand(0);
416 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
417 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
419 TII->getOperandIdx(Opcode, R600Operands::SRC0),
420 TII->getOperandIdx(Opcode, R600Operands::SRC1),
421 TII->getOperandIdx(Opcode, R600Operands::SRC2)
424 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
425 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
426 TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
429 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
430 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
431 TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
434 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
435 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
439 // Gather constants values
440 std::vector<unsigned> Consts;
441 for (unsigned j = 0; j < 3; j++) {
442 int SrcIdx = OperandIdx[j];
445 if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Ops[SrcIdx - 1])) {
446 if (Reg->getReg() == AMDGPU::ALU_CONST) {
447 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Ops[SelIdx[j] - 1]);
448 Consts.push_back(Cst->getZExtValue());
453 for (unsigned i = 0; i < 3; i++) {
454 if (OperandIdx[i] < 0)
456 SDValue &Src = Ops[OperandIdx[i] - 1];
457 SDValue &Sel = Ops[SelIdx[i] - 1];
458 SDValue &Neg = Ops[NegIdx[i] - 1];
460 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
461 if (FoldOperand(Src, Sel, Neg, Abs, TII, Consts))
467 bool AMDGPUDAGToDAGISel::FoldDotOperands(unsigned Opcode,
468 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
470 TII->getOperandIdx(Opcode, R600Operands::SRC0_X),
471 TII->getOperandIdx(Opcode, R600Operands::SRC0_Y),
472 TII->getOperandIdx(Opcode, R600Operands::SRC0_Z),
473 TII->getOperandIdx(Opcode, R600Operands::SRC0_W),
474 TII->getOperandIdx(Opcode, R600Operands::SRC1_X),
475 TII->getOperandIdx(Opcode, R600Operands::SRC1_Y),
476 TII->getOperandIdx(Opcode, R600Operands::SRC1_Z),
477 TII->getOperandIdx(Opcode, R600Operands::SRC1_W)
480 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_X),
481 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_Y),
482 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_Z),
483 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL_W),
484 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_X),
485 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_Y),
486 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_Z),
487 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL_W)
490 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_X),
491 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_Y),
492 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_Z),
493 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG_W),
494 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_X),
495 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_Y),
496 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_Z),
497 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG_W)
500 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_X),
501 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_Y),
502 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_Z),
503 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS_W),
504 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_X),
505 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_Y),
506 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_Z),
507 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS_W)
510 // Gather constants values
511 std::vector<unsigned> Consts;
512 for (unsigned j = 0; j < 8; j++) {
513 int SrcIdx = OperandIdx[j];
516 if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Ops[SrcIdx - 1])) {
517 if (Reg->getReg() == AMDGPU::ALU_CONST) {
518 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Ops[SelIdx[j] - 1]);
519 Consts.push_back(Cst->getZExtValue());
524 for (unsigned i = 0; i < 8; i++) {
525 if (OperandIdx[i] < 0)
527 SDValue &Src = Ops[OperandIdx[i] - 1];
528 SDValue &Sel = Ops[SelIdx[i] - 1];
529 SDValue &Neg = Ops[NegIdx[i] - 1];
530 SDValue &Abs = Ops[AbsIdx[i] - 1];
531 if (FoldOperand(Src, Sel, Neg, Abs, TII, Consts))
537 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
541 Type *ptrType = ptr->getType();
542 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
545 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
546 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
549 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
550 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
551 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
552 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
555 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
556 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
559 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
560 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
563 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) const {
564 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
568 const DataLayout *DL = TM.getDataLayout();
569 MachineMemOperand *MMO = N->getMemOperand();
570 const Value *V = MMO->getValue();
571 const Value *BV = GetUnderlyingObject(V, DL, 0);
574 && ((V && dyn_cast<GlobalValue>(V))
575 || (BV && dyn_cast<GlobalValue>(
576 GetUnderlyingObject(MMO->getValue(), DL, 0))))) {
577 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
583 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
584 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
587 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
588 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
591 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
592 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
595 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
596 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
599 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
600 MachineMemOperand *MMO = N->getMemOperand();
601 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
603 const Value *V = MMO->getValue();
604 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
605 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
613 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
614 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
615 // Check to make sure we are not a constant pool load or a constant load
616 // that is marked as a private load
617 if (isCPLoad(N) || isConstantLoad(N, -1)) {
621 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
622 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
623 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
624 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
625 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
626 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
632 const char *AMDGPUDAGToDAGISel::getPassName() const {
633 return "AMDGPU DAG->DAG Pattern Instruction Selection";
641 ///==== AMDGPU Functions ====///
643 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
645 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
646 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
652 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
653 SDValue& BaseReg, SDValue &Offset) {
654 if (!dyn_cast<ConstantSDNode>(Addr)) {
656 Offset = CurDAG->getIntPtrConstant(0, true);
662 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
664 ConstantSDNode * IMMOffset;
666 if (Addr.getOpcode() == ISD::ADD
667 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
668 && isInt<16>(IMMOffset->getZExtValue())) {
670 Base = Addr.getOperand(0);
671 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
673 // If the pointer address is constant, we can move it to the offset field.
674 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
675 && isInt<16>(IMMOffset->getZExtValue())) {
676 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
677 SDLoc(CurDAG->getEntryNode()),
678 AMDGPU::ZERO, MVT::i32);
679 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
683 // Default case, no offset
685 Offset = CurDAG->getTargetConstant(0, MVT::i32);
689 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
693 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
694 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
695 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
696 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
697 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
698 Base = Addr.getOperand(0);
699 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
702 Offset = CurDAG->getTargetConstant(0, MVT::i32);
708 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
710 if (Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
714 // Go over all selected nodes and try to fold them a bit more
715 const AMDGPUTargetLowering& Lowering = (*(const AMDGPUTargetLowering*)TLI);
716 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
717 E = CurDAG->allnodes_end(); I != E; ++I) {
720 switch (Node->getOpcode()) {
721 // Fix the register class in copy to CopyToReg nodes - ISel will always
722 // use SReg classes for 64-bit copies, but this is not always what we want.
723 case ISD::CopyToReg: {
724 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
725 SDValue Val = Node->getOperand(2);
726 const TargetRegisterClass *RC = RegInfo->getRegClass(Reg);
727 if (RC != &AMDGPU::SReg_64RegClass) {
731 if (!Val.getNode()->isMachineOpcode() ||
732 Val.getNode()->getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
736 const MCInstrDesc Desc = TM.getInstrInfo()->get(Val.getNode()->getMachineOpcode());
737 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
738 RegInfo->setRegClass(Reg, TRI->getRegClass(Desc.OpInfo[0].RegClass));
743 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
747 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
748 if (ResNode != Node) {
749 ReplaceUses(Node, ResNode);