1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDILDevices.h"
18 #include "R600InstrInfo.h"
19 #include "llvm/ADT/ValueMap.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
29 //===----------------------------------------------------------------------===//
30 // Instruction Selector Implementation
31 //===----------------------------------------------------------------------===//
34 /// AMDGPU specific code to select AMDGPU machine instructions for
35 /// SelectionDAG operations.
36 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
37 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
38 // make the right decision when generating code for different targets.
39 const AMDGPUSubtarget &Subtarget;
41 AMDGPUDAGToDAGISel(TargetMachine &TM);
42 virtual ~AMDGPUDAGToDAGISel();
44 SDNode *Select(SDNode *N);
45 virtual const char *getPassName() const;
48 inline SDValue getSmallIPtrImm(unsigned Imm);
49 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
51 // Complex pattern selectors
52 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
53 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
54 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
56 static bool checkType(const Value *ptr, unsigned int addrspace);
57 static const Value *getBasePointerValue(const Value *V);
59 static bool isGlobalStore(const StoreSDNode *N);
60 static bool isPrivateStore(const StoreSDNode *N);
61 static bool isLocalStore(const StoreSDNode *N);
62 static bool isRegionStore(const StoreSDNode *N);
64 static bool isCPLoad(const LoadSDNode *N);
65 static bool isConstantLoad(const LoadSDNode *N, int cbID);
66 static bool isGlobalLoad(const LoadSDNode *N);
67 static bool isParamLoad(const LoadSDNode *N);
68 static bool isPrivateLoad(const LoadSDNode *N);
69 static bool isLocalLoad(const LoadSDNode *N);
70 static bool isRegionLoad(const LoadSDNode *N);
72 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
73 bool SelectGlobalValueVariableOffset(SDValue Addr,
74 SDValue &BaseReg, SDValue& Offset);
75 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
76 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
78 // Include the pieces autogenerated from the target description.
79 #include "AMDGPUGenDAGISel.inc"
81 } // end anonymous namespace
83 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
84 // DAG, ready for instruction scheduling.
85 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
87 return new AMDGPUDAGToDAGISel(TM);
90 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
92 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
95 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
98 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
99 return CurDAG->getTargetConstant(Imm, MVT::i32);
102 bool AMDGPUDAGToDAGISel::SelectADDRParam(
103 SDValue Addr, SDValue& R1, SDValue& R2) {
105 if (Addr.getOpcode() == ISD::FrameIndex) {
106 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
107 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
108 R2 = CurDAG->getTargetConstant(0, MVT::i32);
111 R2 = CurDAG->getTargetConstant(0, MVT::i32);
113 } else if (Addr.getOpcode() == ISD::ADD) {
114 R1 = Addr.getOperand(0);
115 R2 = Addr.getOperand(1);
118 R2 = CurDAG->getTargetConstant(0, MVT::i32);
123 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
124 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
125 Addr.getOpcode() == ISD::TargetGlobalAddress) {
128 return SelectADDRParam(Addr, R1, R2);
132 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
133 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
134 Addr.getOpcode() == ISD::TargetGlobalAddress) {
138 if (Addr.getOpcode() == ISD::FrameIndex) {
139 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
140 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
141 R2 = CurDAG->getTargetConstant(0, MVT::i64);
144 R2 = CurDAG->getTargetConstant(0, MVT::i64);
146 } else if (Addr.getOpcode() == ISD::ADD) {
147 R1 = Addr.getOperand(0);
148 R2 = Addr.getOperand(1);
151 R2 = CurDAG->getTargetConstant(0, MVT::i64);
156 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
157 unsigned int Opc = N->getOpcode();
158 if (N->isMachineOpcode()) {
159 return NULL; // Already selected.
163 case ISD::ConstantFP:
164 case ISD::Constant: {
165 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
166 // XXX: Custom immediate lowering not implemented yet. Instead we use
167 // pseudo instructions defined in SIInstructions.td
168 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
171 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
173 uint64_t ImmValue = 0;
174 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
176 if (N->getOpcode() == ISD::ConstantFP) {
177 // XXX: 64-bit Immediates not supported yet
178 assert(N->getValueType(0) != MVT::f64);
180 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
181 APFloat Value = C->getValueAPF();
182 float FloatValue = Value.convertToFloat();
183 if (FloatValue == 0.0) {
184 ImmReg = AMDGPU::ZERO;
185 } else if (FloatValue == 0.5) {
186 ImmReg = AMDGPU::HALF;
187 } else if (FloatValue == 1.0) {
188 ImmReg = AMDGPU::ONE;
190 ImmValue = Value.bitcastToAPInt().getZExtValue();
193 // XXX: 64-bit Immediates not supported yet
194 assert(N->getValueType(0) != MVT::i64);
196 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
197 if (C->getZExtValue() == 0) {
198 ImmReg = AMDGPU::ZERO;
199 } else if (C->getZExtValue() == 1) {
200 ImmReg = AMDGPU::ONE_INT;
202 ImmValue = C->getZExtValue();
206 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
207 Use != SDNode::use_end(); Use = Next) {
208 Next = llvm::next(Use);
209 std::vector<SDValue> Ops;
210 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
211 Ops.push_back(Use->getOperand(i));
214 if (!Use->isMachineOpcode()) {
215 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
216 // We can only use literal constants (e.g. AMDGPU::ZERO,
217 // AMDGPU::ONE, etc) in machine opcodes.
221 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
222 (TII->get(Use->getMachineOpcode()).TSFlags &
223 R600_InstFlag::VECTOR)) {
227 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
228 assert(ImmIdx != -1);
230 // subtract one from ImmIdx, because the DST operand is usually index
231 // 0 for MachineInstrs, but we have no DST in the Ops vector.
234 // Check that we aren't already using an immediate.
235 // XXX: It's possible for an instruction to have more than one
236 // immediate operand, but this is not supported yet.
237 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
238 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
241 if (C->getZExtValue() != 0) {
242 // This instruction is already using an immediate.
246 // Set the immediate value
247 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
250 // Set the immediate register
251 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
253 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
258 SDNode *Result = SelectCode(N);
260 // Fold operands of selected node
262 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
263 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
264 const R600InstrInfo *TII =
265 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
266 if (Result && Result->isMachineOpcode() &&
267 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
268 && TII->isALUInstr(Result->getMachineOpcode())) {
269 // Fold FNEG/FABS/CONST_ADDRESS
270 // TODO: Isel can generate multiple MachineInst, we need to recursively
272 bool IsModified = false;
274 std::vector<SDValue> Ops;
275 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
278 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
280 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
282 } while (IsModified);
284 // If node has a single use which is CLAMP_R600, folds it
285 if (Result->hasOneUse() && Result->isMachineOpcode()) {
286 SDNode *PotentialClamp = *Result->use_begin();
287 if (PotentialClamp->isMachineOpcode() &&
288 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
290 TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
291 std::vector<SDValue> Ops;
292 unsigned NumOp = Result->getNumOperands();
293 for (unsigned i = 0; i < NumOp; ++i) {
294 Ops.push_back(Result->getOperand(i));
296 Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
297 Result = CurDAG->SelectNodeTo(PotentialClamp,
298 Result->getMachineOpcode(), PotentialClamp->getVTList(),
308 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
309 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
311 TII->getOperandIdx(Opcode, R600Operands::SRC0),
312 TII->getOperandIdx(Opcode, R600Operands::SRC1),
313 TII->getOperandIdx(Opcode, R600Operands::SRC2)
316 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
317 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
318 TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
321 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
322 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
323 TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
326 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
327 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
331 for (unsigned i = 0; i < 3; i++) {
332 if (OperandIdx[i] < 0)
334 SDValue Operand = Ops[OperandIdx[i] - 1];
335 switch (Operand.getOpcode()) {
336 case AMDGPUISD::CONST_ADDRESS: {
340 if (!Operand.getValueType().isVector() &&
341 SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) {
342 Ops[OperandIdx[i] - 1] = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
343 Ops[SelIdx[i] - 1] = CstOffset;
351 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
352 Ops[NegIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
357 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
358 Ops[AbsIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
361 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
370 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
374 Type *ptrType = ptr->getType();
375 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
378 const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
382 const Value *ret = NULL;
383 ValueMap<const Value *, bool> ValueBitMap;
384 std::queue<const Value *, std::list<const Value *> > ValueQueue;
386 while (!ValueQueue.empty()) {
387 V = ValueQueue.front();
388 if (ValueBitMap.find(V) == ValueBitMap.end()) {
389 ValueBitMap[V] = true;
390 if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
393 } else if (dyn_cast<GlobalVariable>(V)) {
396 } else if (dyn_cast<Constant>(V)) {
397 const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
399 ValueQueue.push(CE->getOperand(0));
401 } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
404 } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
405 uint32_t numOps = I->getNumOperands();
406 for (uint32_t x = 0; x < numOps; ++x) {
407 ValueQueue.push(I->getOperand(x));
410 assert(!"Found a Value that we didn't know how to handle!");
418 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
419 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
422 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
423 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
424 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
425 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
428 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
429 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
432 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
433 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
436 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
437 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
440 MachineMemOperand *MMO = N->getMemOperand();
441 const Value *V = MMO->getValue();
442 const Value *BV = getBasePointerValue(V);
445 && ((V && dyn_cast<GlobalValue>(V))
446 || (BV && dyn_cast<GlobalValue>(
447 getBasePointerValue(MMO->getValue()))))) {
448 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
454 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
455 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
458 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
459 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
462 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
463 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
466 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
467 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
470 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
471 MachineMemOperand *MMO = N->getMemOperand();
472 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
474 const Value *V = MMO->getValue();
475 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
476 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
484 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
485 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
486 // Check to make sure we are not a constant pool load or a constant load
487 // that is marked as a private load
488 if (isCPLoad(N) || isConstantLoad(N, -1)) {
492 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
493 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
494 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
495 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
496 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
497 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
503 const char *AMDGPUDAGToDAGISel::getPassName() const {
504 return "AMDGPU DAG->DAG Pattern Instruction Selection";
512 ///==== AMDGPU Functions ====///
514 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
516 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
517 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
523 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
524 SDValue& BaseReg, SDValue &Offset) {
525 if (!dyn_cast<ConstantSDNode>(Addr)) {
527 Offset = CurDAG->getIntPtrConstant(0, true);
533 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
535 ConstantSDNode * IMMOffset;
537 if (Addr.getOpcode() == ISD::ADD
538 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
539 && isInt<16>(IMMOffset->getZExtValue())) {
541 Base = Addr.getOperand(0);
542 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
544 // If the pointer address is constant, we can move it to the offset field.
545 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
546 && isInt<16>(IMMOffset->getZExtValue())) {
547 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
548 CurDAG->getEntryNode().getDebugLoc(),
549 AMDGPU::ZERO, MVT::i32);
550 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
554 // Default case, no offset
556 Offset = CurDAG->getTargetConstant(0, MVT::i32);
560 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
564 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
565 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
566 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
567 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
568 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
569 Base = Addr.getOperand(0);
570 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
573 Offset = CurDAG->getTargetConstant(0, MVT::i32);