1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDILDevices.h"
18 #include "R600InstrInfo.h"
19 #include "SIISelLowering.h"
20 #include "llvm/ADT/ValueMap.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Support/Compiler.h"
30 //===----------------------------------------------------------------------===//
31 // Instruction Selector Implementation
32 //===----------------------------------------------------------------------===//
35 /// AMDGPU specific code to select AMDGPU machine instructions for
36 /// SelectionDAG operations.
37 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
38 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
39 // make the right decision when generating code for different targets.
40 const AMDGPUSubtarget &Subtarget;
42 AMDGPUDAGToDAGISel(TargetMachine &TM);
43 virtual ~AMDGPUDAGToDAGISel();
45 SDNode *Select(SDNode *N);
46 virtual const char *getPassName() const;
47 virtual void PostprocessISelDAG();
50 inline SDValue getSmallIPtrImm(unsigned Imm);
51 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
53 // Complex pattern selectors
54 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
55 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
56 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
58 static bool checkType(const Value *ptr, unsigned int addrspace);
59 static const Value *getBasePointerValue(const Value *V);
61 static bool isGlobalStore(const StoreSDNode *N);
62 static bool isPrivateStore(const StoreSDNode *N);
63 static bool isLocalStore(const StoreSDNode *N);
64 static bool isRegionStore(const StoreSDNode *N);
66 static bool isCPLoad(const LoadSDNode *N);
67 static bool isConstantLoad(const LoadSDNode *N, int cbID);
68 static bool isGlobalLoad(const LoadSDNode *N);
69 static bool isParamLoad(const LoadSDNode *N);
70 static bool isPrivateLoad(const LoadSDNode *N);
71 static bool isLocalLoad(const LoadSDNode *N);
72 static bool isRegionLoad(const LoadSDNode *N);
74 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
75 bool SelectGlobalValueVariableOffset(SDValue Addr,
76 SDValue &BaseReg, SDValue& Offset);
77 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
78 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
80 // Include the pieces autogenerated from the target description.
81 #include "AMDGPUGenDAGISel.inc"
83 } // end anonymous namespace
85 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
86 // DAG, ready for instruction scheduling.
87 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
89 return new AMDGPUDAGToDAGISel(TM);
92 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
94 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
97 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
100 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
101 return CurDAG->getTargetConstant(Imm, MVT::i32);
104 bool AMDGPUDAGToDAGISel::SelectADDRParam(
105 SDValue Addr, SDValue& R1, SDValue& R2) {
107 if (Addr.getOpcode() == ISD::FrameIndex) {
108 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
109 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
110 R2 = CurDAG->getTargetConstant(0, MVT::i32);
113 R2 = CurDAG->getTargetConstant(0, MVT::i32);
115 } else if (Addr.getOpcode() == ISD::ADD) {
116 R1 = Addr.getOperand(0);
117 R2 = Addr.getOperand(1);
120 R2 = CurDAG->getTargetConstant(0, MVT::i32);
125 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
126 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
127 Addr.getOpcode() == ISD::TargetGlobalAddress) {
130 return SelectADDRParam(Addr, R1, R2);
134 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
135 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
136 Addr.getOpcode() == ISD::TargetGlobalAddress) {
140 if (Addr.getOpcode() == ISD::FrameIndex) {
141 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
142 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
143 R2 = CurDAG->getTargetConstant(0, MVT::i64);
146 R2 = CurDAG->getTargetConstant(0, MVT::i64);
148 } else if (Addr.getOpcode() == ISD::ADD) {
149 R1 = Addr.getOperand(0);
150 R2 = Addr.getOperand(1);
153 R2 = CurDAG->getTargetConstant(0, MVT::i64);
158 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
159 unsigned int Opc = N->getOpcode();
160 if (N->isMachineOpcode()) {
161 return NULL; // Already selected.
165 case ISD::BUILD_VECTOR: {
166 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
167 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
170 // BUILD_VECTOR is usually lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
171 // that adds a 128 bits reg copy when going through TwoAddressInstructions
172 // pass. We want to avoid 128 bits copies as much as possible because they
173 // can't be bundled by our scheduler.
174 SDValue RegSeqArgs[9] = {
175 CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32),
176 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
177 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
178 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
179 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
181 bool IsRegSeq = true;
182 for (unsigned i = 0; i < N->getNumOperands(); i++) {
183 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
187 RegSeqArgs[2 * i + 1] = N->getOperand(i);
191 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
192 RegSeqArgs, 2 * N->getNumOperands() + 1);
194 case ISD::BUILD_PAIR: {
195 SDValue RC, SubReg0, SubReg1;
196 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
197 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
200 if (N->getValueType(0) == MVT::i128) {
201 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
202 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
203 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
204 } else if (N->getValueType(0) == MVT::i64) {
205 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
206 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
207 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
209 llvm_unreachable("Unhandled value type for BUILD_PAIR");
211 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
212 N->getOperand(1), SubReg1 };
213 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
214 SDLoc(N), N->getValueType(0), Ops);
217 case ISD::ConstantFP:
218 case ISD::Constant: {
219 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
220 // XXX: Custom immediate lowering not implemented yet. Instead we use
221 // pseudo instructions defined in SIInstructions.td
222 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
225 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
227 uint64_t ImmValue = 0;
228 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
230 if (N->getOpcode() == ISD::ConstantFP) {
231 // XXX: 64-bit Immediates not supported yet
232 assert(N->getValueType(0) != MVT::f64);
234 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
235 APFloat Value = C->getValueAPF();
236 float FloatValue = Value.convertToFloat();
237 if (FloatValue == 0.0) {
238 ImmReg = AMDGPU::ZERO;
239 } else if (FloatValue == 0.5) {
240 ImmReg = AMDGPU::HALF;
241 } else if (FloatValue == 1.0) {
242 ImmReg = AMDGPU::ONE;
244 ImmValue = Value.bitcastToAPInt().getZExtValue();
247 // XXX: 64-bit Immediates not supported yet
248 assert(N->getValueType(0) != MVT::i64);
250 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
251 if (C->getZExtValue() == 0) {
252 ImmReg = AMDGPU::ZERO;
253 } else if (C->getZExtValue() == 1) {
254 ImmReg = AMDGPU::ONE_INT;
256 ImmValue = C->getZExtValue();
260 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
261 Use != SDNode::use_end(); Use = Next) {
262 Next = llvm::next(Use);
263 std::vector<SDValue> Ops;
264 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
265 Ops.push_back(Use->getOperand(i));
268 if (!Use->isMachineOpcode()) {
269 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
270 // We can only use literal constants (e.g. AMDGPU::ZERO,
271 // AMDGPU::ONE, etc) in machine opcodes.
275 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
276 (TII->get(Use->getMachineOpcode()).TSFlags &
277 R600_InstFlag::VECTOR)) {
281 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
282 assert(ImmIdx != -1);
284 // subtract one from ImmIdx, because the DST operand is usually index
285 // 0 for MachineInstrs, but we have no DST in the Ops vector.
288 // Check that we aren't already using an immediate.
289 // XXX: It's possible for an instruction to have more than one
290 // immediate operand, but this is not supported yet.
291 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
292 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
295 if (C->getZExtValue() != 0) {
296 // This instruction is already using an immediate.
300 // Set the immediate value
301 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
304 // Set the immediate register
305 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
307 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
312 SDNode *Result = SelectCode(N);
314 // Fold operands of selected node
316 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
317 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
318 const R600InstrInfo *TII =
319 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
320 if (Result && Result->isMachineOpcode() &&
321 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
322 && TII->isALUInstr(Result->getMachineOpcode())) {
323 // Fold FNEG/FABS/CONST_ADDRESS
324 // TODO: Isel can generate multiple MachineInst, we need to recursively
326 bool IsModified = false;
328 std::vector<SDValue> Ops;
329 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
332 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
334 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
336 } while (IsModified);
338 // If node has a single use which is CLAMP_R600, folds it
339 if (Result->hasOneUse() && Result->isMachineOpcode()) {
340 SDNode *PotentialClamp = *Result->use_begin();
341 if (PotentialClamp->isMachineOpcode() &&
342 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
344 TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
345 std::vector<SDValue> Ops;
346 unsigned NumOp = Result->getNumOperands();
347 for (unsigned i = 0; i < NumOp; ++i) {
348 Ops.push_back(Result->getOperand(i));
350 Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
351 Result = CurDAG->SelectNodeTo(PotentialClamp,
352 Result->getMachineOpcode(), PotentialClamp->getVTList(),
362 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
363 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
365 TII->getOperandIdx(Opcode, R600Operands::SRC0),
366 TII->getOperandIdx(Opcode, R600Operands::SRC1),
367 TII->getOperandIdx(Opcode, R600Operands::SRC2)
370 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
371 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
372 TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
375 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
376 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
377 TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
380 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
381 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
385 for (unsigned i = 0; i < 3; i++) {
386 if (OperandIdx[i] < 0)
388 SDValue Operand = Ops[OperandIdx[i] - 1];
389 switch (Operand.getOpcode()) {
390 case AMDGPUISD::CONST_ADDRESS: {
392 if (Operand.getValueType().isVector() ||
393 !SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset))
396 // Gather others constants values
397 std::vector<unsigned> Consts;
398 for (unsigned j = 0; j < 3; j++) {
399 int SrcIdx = OperandIdx[j];
402 if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Ops[SrcIdx - 1])) {
403 if (Reg->getReg() == AMDGPU::ALU_CONST) {
404 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Ops[SelIdx[j] - 1]);
405 Consts.push_back(Cst->getZExtValue());
410 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
411 Consts.push_back(Cst->getZExtValue());
412 if (!TII->fitsConstReadLimitations(Consts))
415 Ops[OperandIdx[i] - 1] = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
416 Ops[SelIdx[i] - 1] = CstOffset;
422 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
423 Ops[NegIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
428 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
429 Ops[AbsIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
432 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
441 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
445 Type *ptrType = ptr->getType();
446 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
449 const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
453 const Value *ret = NULL;
454 ValueMap<const Value *, bool> ValueBitMap;
455 std::queue<const Value *, std::list<const Value *> > ValueQueue;
457 while (!ValueQueue.empty()) {
458 V = ValueQueue.front();
459 if (ValueBitMap.find(V) == ValueBitMap.end()) {
460 ValueBitMap[V] = true;
461 if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
464 } else if (dyn_cast<GlobalVariable>(V)) {
467 } else if (dyn_cast<Constant>(V)) {
468 const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
470 ValueQueue.push(CE->getOperand(0));
472 } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
475 } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
476 uint32_t numOps = I->getNumOperands();
477 for (uint32_t x = 0; x < numOps; ++x) {
478 ValueQueue.push(I->getOperand(x));
481 assert(!"Found a Value that we didn't know how to handle!");
489 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
490 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
493 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
494 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
495 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
496 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
499 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
500 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
503 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
504 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
507 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
508 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
511 MachineMemOperand *MMO = N->getMemOperand();
512 const Value *V = MMO->getValue();
513 const Value *BV = getBasePointerValue(V);
516 && ((V && dyn_cast<GlobalValue>(V))
517 || (BV && dyn_cast<GlobalValue>(
518 getBasePointerValue(MMO->getValue()))))) {
519 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
525 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
526 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
529 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
530 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
533 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
534 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
537 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
538 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
541 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
542 MachineMemOperand *MMO = N->getMemOperand();
543 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
545 const Value *V = MMO->getValue();
546 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
547 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
555 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
556 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
557 // Check to make sure we are not a constant pool load or a constant load
558 // that is marked as a private load
559 if (isCPLoad(N) || isConstantLoad(N, -1)) {
563 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
564 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
565 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
566 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
567 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
568 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
574 const char *AMDGPUDAGToDAGISel::getPassName() const {
575 return "AMDGPU DAG->DAG Pattern Instruction Selection";
583 ///==== AMDGPU Functions ====///
585 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
587 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
588 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
594 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
595 SDValue& BaseReg, SDValue &Offset) {
596 if (!dyn_cast<ConstantSDNode>(Addr)) {
598 Offset = CurDAG->getIntPtrConstant(0, true);
604 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
606 ConstantSDNode * IMMOffset;
608 if (Addr.getOpcode() == ISD::ADD
609 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
610 && isInt<16>(IMMOffset->getZExtValue())) {
612 Base = Addr.getOperand(0);
613 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
615 // If the pointer address is constant, we can move it to the offset field.
616 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
617 && isInt<16>(IMMOffset->getZExtValue())) {
618 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
619 SDLoc(CurDAG->getEntryNode()),
620 AMDGPU::ZERO, MVT::i32);
621 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
625 // Default case, no offset
627 Offset = CurDAG->getTargetConstant(0, MVT::i32);
631 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
635 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
636 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
637 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
638 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
639 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
640 Base = Addr.getOperand(0);
641 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
644 Offset = CurDAG->getTargetConstant(0, MVT::i32);
650 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
652 // Go over all selected nodes and try to fold them a bit more
653 const AMDGPUTargetLowering& Lowering = ((const AMDGPUTargetLowering&)TLI);
654 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
655 E = CurDAG->allnodes_end(); I != E; ++I) {
657 MachineSDNode *Node = dyn_cast<MachineSDNode>(I);
661 SDNode *ResNode = Lowering.PostISelFolding(Node, *CurDAG);
663 ReplaceUses(Node, ResNode);