1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDILDevices.h"
18 #include "R600InstrInfo.h"
19 #include "llvm/ADT/ValueMap.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
29 //===----------------------------------------------------------------------===//
30 // Instruction Selector Implementation
31 //===----------------------------------------------------------------------===//
34 /// AMDGPU specific code to select AMDGPU machine instructions for
35 /// SelectionDAG operations.
36 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
37 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
38 // make the right decision when generating code for different targets.
39 const AMDGPUSubtarget &Subtarget;
41 AMDGPUDAGToDAGISel(TargetMachine &TM);
42 virtual ~AMDGPUDAGToDAGISel();
44 SDNode *Select(SDNode *N);
45 virtual const char *getPassName() const;
46 virtual void PostprocessISelDAG();
49 inline SDValue getSmallIPtrImm(unsigned Imm);
50 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
52 // Complex pattern selectors
53 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
54 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
55 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
57 static bool checkType(const Value *ptr, unsigned int addrspace);
58 static const Value *getBasePointerValue(const Value *V);
60 static bool isGlobalStore(const StoreSDNode *N);
61 static bool isPrivateStore(const StoreSDNode *N);
62 static bool isLocalStore(const StoreSDNode *N);
63 static bool isRegionStore(const StoreSDNode *N);
65 static bool isCPLoad(const LoadSDNode *N);
66 static bool isConstantLoad(const LoadSDNode *N, int cbID);
67 static bool isGlobalLoad(const LoadSDNode *N);
68 static bool isParamLoad(const LoadSDNode *N);
69 static bool isPrivateLoad(const LoadSDNode *N);
70 static bool isLocalLoad(const LoadSDNode *N);
71 static bool isRegionLoad(const LoadSDNode *N);
73 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
74 bool SelectGlobalValueVariableOffset(SDValue Addr,
75 SDValue &BaseReg, SDValue& Offset);
76 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
77 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
79 // Include the pieces autogenerated from the target description.
80 #include "AMDGPUGenDAGISel.inc"
82 } // end anonymous namespace
84 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
85 // DAG, ready for instruction scheduling.
86 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
88 return new AMDGPUDAGToDAGISel(TM);
91 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
93 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
96 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
99 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
100 return CurDAG->getTargetConstant(Imm, MVT::i32);
103 bool AMDGPUDAGToDAGISel::SelectADDRParam(
104 SDValue Addr, SDValue& R1, SDValue& R2) {
106 if (Addr.getOpcode() == ISD::FrameIndex) {
107 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
108 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
109 R2 = CurDAG->getTargetConstant(0, MVT::i32);
112 R2 = CurDAG->getTargetConstant(0, MVT::i32);
114 } else if (Addr.getOpcode() == ISD::ADD) {
115 R1 = Addr.getOperand(0);
116 R2 = Addr.getOperand(1);
119 R2 = CurDAG->getTargetConstant(0, MVT::i32);
124 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
125 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
126 Addr.getOpcode() == ISD::TargetGlobalAddress) {
129 return SelectADDRParam(Addr, R1, R2);
133 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
134 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
135 Addr.getOpcode() == ISD::TargetGlobalAddress) {
139 if (Addr.getOpcode() == ISD::FrameIndex) {
140 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
141 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
142 R2 = CurDAG->getTargetConstant(0, MVT::i64);
145 R2 = CurDAG->getTargetConstant(0, MVT::i64);
147 } else if (Addr.getOpcode() == ISD::ADD) {
148 R1 = Addr.getOperand(0);
149 R2 = Addr.getOperand(1);
152 R2 = CurDAG->getTargetConstant(0, MVT::i64);
157 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
158 unsigned int Opc = N->getOpcode();
159 if (N->isMachineOpcode()) {
160 return NULL; // Already selected.
164 case ISD::ConstantFP:
165 case ISD::Constant: {
166 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
167 // XXX: Custom immediate lowering not implemented yet. Instead we use
168 // pseudo instructions defined in SIInstructions.td
169 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
172 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
174 uint64_t ImmValue = 0;
175 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
177 if (N->getOpcode() == ISD::ConstantFP) {
178 // XXX: 64-bit Immediates not supported yet
179 assert(N->getValueType(0) != MVT::f64);
181 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
182 APFloat Value = C->getValueAPF();
183 float FloatValue = Value.convertToFloat();
184 if (FloatValue == 0.0) {
185 ImmReg = AMDGPU::ZERO;
186 } else if (FloatValue == 0.5) {
187 ImmReg = AMDGPU::HALF;
188 } else if (FloatValue == 1.0) {
189 ImmReg = AMDGPU::ONE;
191 ImmValue = Value.bitcastToAPInt().getZExtValue();
194 // XXX: 64-bit Immediates not supported yet
195 assert(N->getValueType(0) != MVT::i64);
197 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
198 if (C->getZExtValue() == 0) {
199 ImmReg = AMDGPU::ZERO;
200 } else if (C->getZExtValue() == 1) {
201 ImmReg = AMDGPU::ONE_INT;
203 ImmValue = C->getZExtValue();
207 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
208 Use != SDNode::use_end(); Use = Next) {
209 Next = llvm::next(Use);
210 std::vector<SDValue> Ops;
211 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
212 Ops.push_back(Use->getOperand(i));
215 if (!Use->isMachineOpcode()) {
216 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
217 // We can only use literal constants (e.g. AMDGPU::ZERO,
218 // AMDGPU::ONE, etc) in machine opcodes.
222 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
223 (TII->get(Use->getMachineOpcode()).TSFlags &
224 R600_InstFlag::VECTOR)) {
228 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
229 assert(ImmIdx != -1);
231 // subtract one from ImmIdx, because the DST operand is usually index
232 // 0 for MachineInstrs, but we have no DST in the Ops vector.
235 // Check that we aren't already using an immediate.
236 // XXX: It's possible for an instruction to have more than one
237 // immediate operand, but this is not supported yet.
238 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
239 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
242 if (C->getZExtValue() != 0) {
243 // This instruction is already using an immediate.
247 // Set the immediate value
248 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
251 // Set the immediate register
252 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
254 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
259 SDNode *Result = SelectCode(N);
261 // Fold operands of selected node
263 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
264 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
265 const R600InstrInfo *TII =
266 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
267 if (Result && Result->isMachineOpcode() &&
268 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
269 && TII->isALUInstr(Result->getMachineOpcode())) {
270 // Fold FNEG/FABS/CONST_ADDRESS
271 // TODO: Isel can generate multiple MachineInst, we need to recursively
273 bool IsModified = false;
275 std::vector<SDValue> Ops;
276 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
279 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
281 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
283 } while (IsModified);
285 // If node has a single use which is CLAMP_R600, folds it
286 if (Result->hasOneUse() && Result->isMachineOpcode()) {
287 SDNode *PotentialClamp = *Result->use_begin();
288 if (PotentialClamp->isMachineOpcode() &&
289 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
291 TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
292 std::vector<SDValue> Ops;
293 unsigned NumOp = Result->getNumOperands();
294 for (unsigned i = 0; i < NumOp; ++i) {
295 Ops.push_back(Result->getOperand(i));
297 Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
298 Result = CurDAG->SelectNodeTo(PotentialClamp,
299 Result->getMachineOpcode(), PotentialClamp->getVTList(),
309 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
310 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
312 TII->getOperandIdx(Opcode, R600Operands::SRC0),
313 TII->getOperandIdx(Opcode, R600Operands::SRC1),
314 TII->getOperandIdx(Opcode, R600Operands::SRC2)
317 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
318 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
319 TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
322 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
323 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
324 TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
327 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
328 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
332 for (unsigned i = 0; i < 3; i++) {
333 if (OperandIdx[i] < 0)
335 SDValue Operand = Ops[OperandIdx[i] - 1];
336 switch (Operand.getOpcode()) {
337 case AMDGPUISD::CONST_ADDRESS: {
341 if (!Operand.getValueType().isVector() &&
342 SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) {
343 Ops[OperandIdx[i] - 1] = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
344 Ops[SelIdx[i] - 1] = CstOffset;
352 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
353 Ops[NegIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
358 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
359 Ops[AbsIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
362 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
371 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
375 Type *ptrType = ptr->getType();
376 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
379 const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
383 const Value *ret = NULL;
384 ValueMap<const Value *, bool> ValueBitMap;
385 std::queue<const Value *, std::list<const Value *> > ValueQueue;
387 while (!ValueQueue.empty()) {
388 V = ValueQueue.front();
389 if (ValueBitMap.find(V) == ValueBitMap.end()) {
390 ValueBitMap[V] = true;
391 if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
394 } else if (dyn_cast<GlobalVariable>(V)) {
397 } else if (dyn_cast<Constant>(V)) {
398 const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
400 ValueQueue.push(CE->getOperand(0));
402 } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
405 } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
406 uint32_t numOps = I->getNumOperands();
407 for (uint32_t x = 0; x < numOps; ++x) {
408 ValueQueue.push(I->getOperand(x));
411 assert(!"Found a Value that we didn't know how to handle!");
419 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
420 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
423 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
424 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
425 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
426 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
429 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
430 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
433 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
434 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
437 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
438 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
441 MachineMemOperand *MMO = N->getMemOperand();
442 const Value *V = MMO->getValue();
443 const Value *BV = getBasePointerValue(V);
446 && ((V && dyn_cast<GlobalValue>(V))
447 || (BV && dyn_cast<GlobalValue>(
448 getBasePointerValue(MMO->getValue()))))) {
449 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
455 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
456 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
459 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
460 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
463 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
464 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
467 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
468 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
471 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
472 MachineMemOperand *MMO = N->getMemOperand();
473 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
475 const Value *V = MMO->getValue();
476 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
477 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
485 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
486 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
487 // Check to make sure we are not a constant pool load or a constant load
488 // that is marked as a private load
489 if (isCPLoad(N) || isConstantLoad(N, -1)) {
493 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
494 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
495 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
496 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
497 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
498 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
504 const char *AMDGPUDAGToDAGISel::getPassName() const {
505 return "AMDGPU DAG->DAG Pattern Instruction Selection";
513 ///==== AMDGPU Functions ====///
515 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
517 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
518 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
524 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
525 SDValue& BaseReg, SDValue &Offset) {
526 if (!dyn_cast<ConstantSDNode>(Addr)) {
528 Offset = CurDAG->getIntPtrConstant(0, true);
534 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
536 ConstantSDNode * IMMOffset;
538 if (Addr.getOpcode() == ISD::ADD
539 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
540 && isInt<16>(IMMOffset->getZExtValue())) {
542 Base = Addr.getOperand(0);
543 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
545 // If the pointer address is constant, we can move it to the offset field.
546 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
547 && isInt<16>(IMMOffset->getZExtValue())) {
548 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
549 CurDAG->getEntryNode().getDebugLoc(),
550 AMDGPU::ZERO, MVT::i32);
551 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
555 // Default case, no offset
557 Offset = CurDAG->getTargetConstant(0, MVT::i32);
561 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
565 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
566 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
567 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
568 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
569 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
570 Base = Addr.getOperand(0);
571 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
574 Offset = CurDAG->getTargetConstant(0, MVT::i32);
580 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
582 // Go over all selected nodes and try to fold them a bit more
583 const AMDGPUTargetLowering& Lowering = ((const AMDGPUTargetLowering&)TLI);
584 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
585 E = CurDAG->allnodes_end(); I != E; ++I) {
587 MachineSDNode *Node = dyn_cast<MachineSDNode>(I);
591 SDNode *ResNode = Lowering.PostISelFolding(Node, *CurDAG);
593 ReplaceUses(Node, ResNode);