1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDILDevices.h"
18 #include "R600InstrInfo.h"
19 #include "SIISelLowering.h"
20 #include "llvm/ADT/ValueMap.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Support/Compiler.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
30 //===----------------------------------------------------------------------===//
31 // Instruction Selector Implementation
32 //===----------------------------------------------------------------------===//
35 /// AMDGPU specific code to select AMDGPU machine instructions for
36 /// SelectionDAG operations.
37 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
38 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
39 // make the right decision when generating code for different targets.
40 const AMDGPUSubtarget &Subtarget;
42 AMDGPUDAGToDAGISel(TargetMachine &TM);
43 virtual ~AMDGPUDAGToDAGISel();
45 SDNode *Select(SDNode *N);
46 virtual const char *getPassName() const;
47 virtual void PostprocessISelDAG();
50 inline SDValue getSmallIPtrImm(unsigned Imm);
51 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
53 // Complex pattern selectors
54 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
55 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
56 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
58 static bool checkType(const Value *ptr, unsigned int addrspace);
59 static const Value *getBasePointerValue(const Value *V);
61 static bool isGlobalStore(const StoreSDNode *N);
62 static bool isPrivateStore(const StoreSDNode *N);
63 static bool isLocalStore(const StoreSDNode *N);
64 static bool isRegionStore(const StoreSDNode *N);
66 static bool isCPLoad(const LoadSDNode *N);
67 static bool isConstantLoad(const LoadSDNode *N, int cbID);
68 static bool isGlobalLoad(const LoadSDNode *N);
69 static bool isParamLoad(const LoadSDNode *N);
70 static bool isPrivateLoad(const LoadSDNode *N);
71 static bool isLocalLoad(const LoadSDNode *N);
72 static bool isRegionLoad(const LoadSDNode *N);
74 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
75 bool SelectGlobalValueVariableOffset(SDValue Addr,
76 SDValue &BaseReg, SDValue& Offset);
77 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
78 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
80 // Include the pieces autogenerated from the target description.
81 #include "AMDGPUGenDAGISel.inc"
83 } // end anonymous namespace
85 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
86 // DAG, ready for instruction scheduling.
87 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
89 return new AMDGPUDAGToDAGISel(TM);
92 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
94 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
97 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
100 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
101 return CurDAG->getTargetConstant(Imm, MVT::i32);
104 bool AMDGPUDAGToDAGISel::SelectADDRParam(
105 SDValue Addr, SDValue& R1, SDValue& R2) {
107 if (Addr.getOpcode() == ISD::FrameIndex) {
108 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
109 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
110 R2 = CurDAG->getTargetConstant(0, MVT::i32);
113 R2 = CurDAG->getTargetConstant(0, MVT::i32);
115 } else if (Addr.getOpcode() == ISD::ADD) {
116 R1 = Addr.getOperand(0);
117 R2 = Addr.getOperand(1);
120 R2 = CurDAG->getTargetConstant(0, MVT::i32);
125 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
126 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
127 Addr.getOpcode() == ISD::TargetGlobalAddress) {
130 return SelectADDRParam(Addr, R1, R2);
134 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
135 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
136 Addr.getOpcode() == ISD::TargetGlobalAddress) {
140 if (Addr.getOpcode() == ISD::FrameIndex) {
141 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
142 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
143 R2 = CurDAG->getTargetConstant(0, MVT::i64);
146 R2 = CurDAG->getTargetConstant(0, MVT::i64);
148 } else if (Addr.getOpcode() == ISD::ADD) {
149 R1 = Addr.getOperand(0);
150 R2 = Addr.getOperand(1);
153 R2 = CurDAG->getTargetConstant(0, MVT::i64);
158 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
159 unsigned int Opc = N->getOpcode();
160 if (N->isMachineOpcode()) {
161 return NULL; // Already selected.
165 case ISD::ConstantFP:
166 case ISD::Constant: {
167 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
168 // XXX: Custom immediate lowering not implemented yet. Instead we use
169 // pseudo instructions defined in SIInstructions.td
170 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
173 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
175 uint64_t ImmValue = 0;
176 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
178 if (N->getOpcode() == ISD::ConstantFP) {
179 // XXX: 64-bit Immediates not supported yet
180 assert(N->getValueType(0) != MVT::f64);
182 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
183 APFloat Value = C->getValueAPF();
184 float FloatValue = Value.convertToFloat();
185 if (FloatValue == 0.0) {
186 ImmReg = AMDGPU::ZERO;
187 } else if (FloatValue == 0.5) {
188 ImmReg = AMDGPU::HALF;
189 } else if (FloatValue == 1.0) {
190 ImmReg = AMDGPU::ONE;
192 ImmValue = Value.bitcastToAPInt().getZExtValue();
195 // XXX: 64-bit Immediates not supported yet
196 assert(N->getValueType(0) != MVT::i64);
198 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
199 if (C->getZExtValue() == 0) {
200 ImmReg = AMDGPU::ZERO;
201 } else if (C->getZExtValue() == 1) {
202 ImmReg = AMDGPU::ONE_INT;
204 ImmValue = C->getZExtValue();
208 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
209 Use != SDNode::use_end(); Use = Next) {
210 Next = llvm::next(Use);
211 std::vector<SDValue> Ops;
212 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
213 Ops.push_back(Use->getOperand(i));
216 if (!Use->isMachineOpcode()) {
217 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
218 // We can only use literal constants (e.g. AMDGPU::ZERO,
219 // AMDGPU::ONE, etc) in machine opcodes.
223 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
224 (TII->get(Use->getMachineOpcode()).TSFlags &
225 R600_InstFlag::VECTOR)) {
229 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
230 assert(ImmIdx != -1);
232 // subtract one from ImmIdx, because the DST operand is usually index
233 // 0 for MachineInstrs, but we have no DST in the Ops vector.
236 // Check that we aren't already using an immediate.
237 // XXX: It's possible for an instruction to have more than one
238 // immediate operand, but this is not supported yet.
239 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
240 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
243 if (C->getZExtValue() != 0) {
244 // This instruction is already using an immediate.
248 // Set the immediate value
249 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
252 // Set the immediate register
253 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
255 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
260 SDNode *Result = SelectCode(N);
262 // Fold operands of selected node
264 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
265 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
266 const R600InstrInfo *TII =
267 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
268 if (Result && Result->isMachineOpcode() &&
269 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
270 && TII->isALUInstr(Result->getMachineOpcode())) {
271 // Fold FNEG/FABS/CONST_ADDRESS
272 // TODO: Isel can generate multiple MachineInst, we need to recursively
274 bool IsModified = false;
276 std::vector<SDValue> Ops;
277 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
280 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
282 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
284 } while (IsModified);
286 // If node has a single use which is CLAMP_R600, folds it
287 if (Result->hasOneUse() && Result->isMachineOpcode()) {
288 SDNode *PotentialClamp = *Result->use_begin();
289 if (PotentialClamp->isMachineOpcode() &&
290 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
292 TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
293 std::vector<SDValue> Ops;
294 unsigned NumOp = Result->getNumOperands();
295 for (unsigned i = 0; i < NumOp; ++i) {
296 Ops.push_back(Result->getOperand(i));
298 Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
299 Result = CurDAG->SelectNodeTo(PotentialClamp,
300 Result->getMachineOpcode(), PotentialClamp->getVTList(),
310 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
311 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
313 TII->getOperandIdx(Opcode, R600Operands::SRC0),
314 TII->getOperandIdx(Opcode, R600Operands::SRC1),
315 TII->getOperandIdx(Opcode, R600Operands::SRC2)
318 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
319 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
320 TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
323 TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
324 TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
325 TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
328 TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
329 TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
333 for (unsigned i = 0; i < 3; i++) {
334 if (OperandIdx[i] < 0)
336 SDValue Operand = Ops[OperandIdx[i] - 1];
337 switch (Operand.getOpcode()) {
338 case AMDGPUISD::CONST_ADDRESS: {
342 if (!Operand.getValueType().isVector() &&
343 SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) {
344 Ops[OperandIdx[i] - 1] = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
345 Ops[SelIdx[i] - 1] = CstOffset;
353 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
354 Ops[NegIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
359 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
360 Ops[AbsIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
363 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
372 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
376 Type *ptrType = ptr->getType();
377 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
380 const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
384 const Value *ret = NULL;
385 ValueMap<const Value *, bool> ValueBitMap;
386 std::queue<const Value *, std::list<const Value *> > ValueQueue;
388 while (!ValueQueue.empty()) {
389 V = ValueQueue.front();
390 if (ValueBitMap.find(V) == ValueBitMap.end()) {
391 ValueBitMap[V] = true;
392 if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
395 } else if (dyn_cast<GlobalVariable>(V)) {
398 } else if (dyn_cast<Constant>(V)) {
399 const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
401 ValueQueue.push(CE->getOperand(0));
403 } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
406 } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
407 uint32_t numOps = I->getNumOperands();
408 for (uint32_t x = 0; x < numOps; ++x) {
409 ValueQueue.push(I->getOperand(x));
412 assert(!"Found a Value that we didn't know how to handle!");
420 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
421 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
424 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
425 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
426 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
427 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
430 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
431 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
434 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
435 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
438 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
439 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
442 MachineMemOperand *MMO = N->getMemOperand();
443 const Value *V = MMO->getValue();
444 const Value *BV = getBasePointerValue(V);
447 && ((V && dyn_cast<GlobalValue>(V))
448 || (BV && dyn_cast<GlobalValue>(
449 getBasePointerValue(MMO->getValue()))))) {
450 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
456 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
457 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
460 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
461 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
464 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
465 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
468 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
469 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
472 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
473 MachineMemOperand *MMO = N->getMemOperand();
474 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
476 const Value *V = MMO->getValue();
477 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
478 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
486 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
487 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
488 // Check to make sure we are not a constant pool load or a constant load
489 // that is marked as a private load
490 if (isCPLoad(N) || isConstantLoad(N, -1)) {
494 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
495 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
496 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
497 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
498 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
499 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
505 const char *AMDGPUDAGToDAGISel::getPassName() const {
506 return "AMDGPU DAG->DAG Pattern Instruction Selection";
514 ///==== AMDGPU Functions ====///
516 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
518 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
519 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
525 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
526 SDValue& BaseReg, SDValue &Offset) {
527 if (!dyn_cast<ConstantSDNode>(Addr)) {
529 Offset = CurDAG->getIntPtrConstant(0, true);
535 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
537 ConstantSDNode * IMMOffset;
539 if (Addr.getOpcode() == ISD::ADD
540 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
541 && isInt<16>(IMMOffset->getZExtValue())) {
543 Base = Addr.getOperand(0);
544 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
546 // If the pointer address is constant, we can move it to the offset field.
547 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
548 && isInt<16>(IMMOffset->getZExtValue())) {
549 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
550 CurDAG->getEntryNode().getDebugLoc(),
551 AMDGPU::ZERO, MVT::i32);
552 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
556 // Default case, no offset
558 Offset = CurDAG->getTargetConstant(0, MVT::i32);
562 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
566 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
567 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
568 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
569 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
570 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
571 Base = Addr.getOperand(0);
572 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
575 Offset = CurDAG->getTargetConstant(0, MVT::i32);
581 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
583 // Go over all selected nodes and try to fold them a bit more
584 const AMDGPUTargetLowering& Lowering = ((const AMDGPUTargetLowering&)TLI);
585 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
586 E = CurDAG->allnodes_end(); I != E; ++I) {
588 MachineSDNode *Node = dyn_cast<MachineSDNode>(I);
592 SDNode *ResNode = Lowering.PostISelFolding(Node, *CurDAG);
594 ReplaceUses(Node, ResNode);