1 //===-- AMDILISelLowering.cpp - AMDIL DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief TargetLowering functions borrowed from AMDIL.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUISelLowering.h"
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDILDevices.h"
19 #include "AMDILIntrinsicInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
38 #include "AMDGPUGenCallingConv.inc"
40 //===----------------------------------------------------------------------===//
41 // TargetLowering Implementation Help Functions End
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
45 // TargetLowering Class Implementation Begins
46 //===----------------------------------------------------------------------===//
47 void AMDGPUTargetLowering::InitAMDILLowering() {
91 size_t NumTypes = sizeof(types) / sizeof(*types);
92 size_t NumFloatTypes = sizeof(FloatTypes) / sizeof(*FloatTypes);
93 size_t NumIntTypes = sizeof(IntTypes) / sizeof(*IntTypes);
94 size_t NumVectorTypes = sizeof(VectorTypes) / sizeof(*VectorTypes);
96 const AMDGPUSubtarget &STM = getTargetMachine().getSubtarget<AMDGPUSubtarget>();
97 // These are the current register classes that are
100 for (unsigned int x = 0; x < NumTypes; ++x) {
101 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
103 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
104 // We cannot sextinreg, expand to shifts
105 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
106 setOperationAction(ISD::SUBE, VT, Expand);
107 setOperationAction(ISD::SUBC, VT, Expand);
108 setOperationAction(ISD::ADDE, VT, Expand);
109 setOperationAction(ISD::ADDC, VT, Expand);
110 setOperationAction(ISD::BRCOND, VT, Custom);
111 setOperationAction(ISD::BR_JT, VT, Expand);
112 setOperationAction(ISD::BRIND, VT, Expand);
113 // TODO: Implement custom UREM/SREM routines
114 setOperationAction(ISD::SREM, VT, Expand);
115 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
116 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
117 if (VT != MVT::i64 && VT != MVT::v2i64) {
118 setOperationAction(ISD::SDIV, VT, Custom);
121 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
122 MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x];
124 // IL does not have these operations for floating point types
125 setOperationAction(ISD::FP_ROUND_INREG, VT, Expand);
126 setOperationAction(ISD::SETOLT, VT, Expand);
127 setOperationAction(ISD::SETOGE, VT, Expand);
128 setOperationAction(ISD::SETOGT, VT, Expand);
129 setOperationAction(ISD::SETOLE, VT, Expand);
130 setOperationAction(ISD::SETULT, VT, Expand);
131 setOperationAction(ISD::SETUGE, VT, Expand);
132 setOperationAction(ISD::SETUGT, VT, Expand);
133 setOperationAction(ISD::SETULE, VT, Expand);
136 for (unsigned int x = 0; x < NumIntTypes; ++x) {
137 MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x];
139 // GPU also does not have divrem function for signed or unsigned
140 setOperationAction(ISD::SDIVREM, VT, Expand);
142 // GPU does not have [S|U]MUL_LOHI functions as a single instruction
143 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
144 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
146 // GPU doesn't have a rotl, rotr, or byteswap instruction
147 setOperationAction(ISD::ROTR, VT, Expand);
148 setOperationAction(ISD::BSWAP, VT, Expand);
150 // GPU doesn't have any counting operators
151 setOperationAction(ISD::CTPOP, VT, Expand);
152 setOperationAction(ISD::CTTZ, VT, Expand);
153 setOperationAction(ISD::CTLZ, VT, Expand);
156 for (unsigned int ii = 0; ii < NumVectorTypes; ++ii) {
157 MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii];
159 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
160 setOperationAction(ISD::SDIVREM, VT, Expand);
161 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
162 // setOperationAction(ISD::VSETCC, VT, Expand);
163 setOperationAction(ISD::SELECT_CC, VT, Expand);
166 if (STM.device()->isSupported(AMDGPUDeviceInfo::LongOps)) {
167 setOperationAction(ISD::MULHU, MVT::i64, Expand);
168 setOperationAction(ISD::MULHU, MVT::v2i64, Expand);
169 setOperationAction(ISD::MULHS, MVT::i64, Expand);
170 setOperationAction(ISD::MULHS, MVT::v2i64, Expand);
171 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
172 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
173 setOperationAction(ISD::Constant , MVT::i64 , Legal);
174 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
175 setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);
176 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand);
177 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Expand);
178 setOperationAction(ISD::ANY_EXTEND, MVT::v2i64, Expand);
180 if (STM.device()->isSupported(AMDGPUDeviceInfo::DoubleOps)) {
181 // we support loading/storing v2f64 but not operations on the type
182 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
183 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
184 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
185 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);
186 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
187 setOperationAction(ISD::ConstantFP , MVT::f64 , Legal);
188 // We want to expand vector conversions into their scalar
190 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
191 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand);
192 setOperationAction(ISD::ZERO_EXTEND, MVT::v2f64, Expand);
193 setOperationAction(ISD::ANY_EXTEND, MVT::v2f64, Expand);
194 setOperationAction(ISD::FABS, MVT::f64, Expand);
195 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
197 // TODO: Fix the UDIV24 algorithm so it works for these
198 // types correctly. This needs vector comparisons
199 // for this to work correctly.
200 setOperationAction(ISD::UDIV, MVT::v2i8, Expand);
201 setOperationAction(ISD::UDIV, MVT::v4i8, Expand);
202 setOperationAction(ISD::UDIV, MVT::v2i16, Expand);
203 setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
205 setOperationAction(ISD::SUBC, MVT::Other, Expand);
206 setOperationAction(ISD::ADDE, MVT::Other, Expand);
207 setOperationAction(ISD::ADDC, MVT::Other, Expand);
208 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
209 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
210 setOperationAction(ISD::BRIND, MVT::Other, Expand);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
214 // Use the default implementation.
215 setOperationAction(ISD::ConstantFP , MVT::f32 , Legal);
216 setOperationAction(ISD::Constant , MVT::i32 , Legal);
218 setSchedulingPreference(Sched::RegPressure);
219 setPow2DivIsCheap(false);
220 setSelectIsExpensive(true);
221 setJumpIsExpensive(true);
223 maxStoresPerMemcpy = 4096;
224 maxStoresPerMemmove = 4096;
225 maxStoresPerMemset = 4096;
230 AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
231 const CallInst &I, unsigned Intrinsic) const {
235 // The backend supports 32 and 64 bit floating point immediates
237 AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
238 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
239 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
247 AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
248 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32
249 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) {
257 // isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
258 // be zero. Op is expected to be a target specific node. Used by DAG
262 AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
266 const SelectionDAG &DAG,
267 unsigned Depth) const {
270 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything
271 switch (Op.getOpcode()) {
274 DAG.ComputeMaskedBits(
280 DAG.ComputeMaskedBits(
285 assert((KnownZero & KnownOne) == 0
286 && "Bits known to be one AND zero?");
287 assert((KnownZero2 & KnownOne2) == 0
288 && "Bits known to be one AND zero?");
289 // Only known if known in both the LHS and RHS
290 KnownOne &= KnownOne2;
291 KnownZero &= KnownZero2;
296 //===----------------------------------------------------------------------===//
297 // Other Lowering Hooks
298 //===----------------------------------------------------------------------===//
301 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
302 EVT OVT = Op.getValueType();
304 if (OVT.getScalarType() == MVT::i64) {
305 DST = LowerSDIV64(Op, DAG);
306 } else if (OVT.getScalarType() == MVT::i32) {
307 DST = LowerSDIV32(Op, DAG);
308 } else if (OVT.getScalarType() == MVT::i16
309 || OVT.getScalarType() == MVT::i8) {
310 DST = LowerSDIV24(Op, DAG);
312 DST = SDValue(Op.getNode(), 0);
318 AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
319 EVT OVT = Op.getValueType();
321 if (OVT.getScalarType() == MVT::i64) {
322 DST = LowerSREM64(Op, DAG);
323 } else if (OVT.getScalarType() == MVT::i32) {
324 DST = LowerSREM32(Op, DAG);
325 } else if (OVT.getScalarType() == MVT::i16) {
326 DST = LowerSREM16(Op, DAG);
327 } else if (OVT.getScalarType() == MVT::i8) {
328 DST = LowerSREM8(Op, DAG);
330 DST = SDValue(Op.getNode(), 0);
336 AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const {
337 SDValue Data = Op.getOperand(0);
338 VTSDNode *BaseType = cast<VTSDNode>(Op.getOperand(1));
339 DebugLoc DL = Op.getDebugLoc();
340 EVT DVT = Data.getValueType();
341 EVT BVT = BaseType->getVT();
342 unsigned baseBits = BVT.getScalarType().getSizeInBits();
343 unsigned srcBits = DVT.isSimple() ? DVT.getScalarType().getSizeInBits() : 1;
344 unsigned shiftBits = srcBits - baseBits;
346 // If the op is less than 32 bits, then it needs to extend to 32bits
347 // so it can properly keep the upper bits valid.
348 EVT IVT = genIntType(32, DVT.isVector() ? DVT.getVectorNumElements() : 1);
349 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data);
350 shiftBits = 32 - baseBits;
353 SDValue Shift = DAG.getConstant(shiftBits, DVT);
354 // Shift left by 'Shift' bits.
355 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift);
356 // Signed shift Right by 'Shift' bits.
357 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
359 // Once the sign extension is done, the op needs to be converted to
360 // its original type.
361 Data = DAG.getSExtOrTrunc(Data, DL, Op.getOperand(0).getValueType());
366 AMDGPUTargetLowering::genIntType(uint32_t size, uint32_t numEle) const {
367 int iSize = (size * numEle);
368 int vEle = (iSize >> ((size == 64) ? 6 : 5));
374 return EVT(MVT::i64);
376 return EVT(MVT::getVectorVT(MVT::i64, vEle));
380 return EVT(MVT::i32);
382 return EVT(MVT::getVectorVT(MVT::i32, vEle));
388 AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
389 SDValue Chain = Op.getOperand(0);
390 SDValue Cond = Op.getOperand(1);
391 SDValue Jump = Op.getOperand(2);
393 Result = DAG.getNode(
394 AMDGPUISD::BRANCH_COND,
402 AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
403 DebugLoc DL = Op.getDebugLoc();
404 EVT OVT = Op.getValueType();
405 SDValue LHS = Op.getOperand(0);
406 SDValue RHS = Op.getOperand(1);
409 if (!OVT.isVector()) {
412 } else if (OVT.getVectorNumElements() == 2) {
415 } else if (OVT.getVectorNumElements() == 4) {
419 unsigned bitsize = OVT.getScalarType().getSizeInBits();
420 // char|short jq = ia ^ ib;
421 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
423 // jq = jq >> (bitsize - 2)
424 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
427 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
430 jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
432 // int ia = (int)LHS;
433 SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
436 SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
438 // float fa = (float)ia;
439 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
441 // float fb = (float)ib;
442 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
444 // float fq = native_divide(fa, fb);
445 SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb);
448 fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
450 // float fqneg = -fq;
451 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
453 // float fr = mad(fqneg, fb, fa);
454 SDValue fr = DAG.getNode(AMDGPUISD::MAD, DL, FLTTY, fqneg, fb, fa);
457 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
460 fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
463 fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
465 // int cv = fr >= fb;
467 if (INTTY == MVT::i32) {
468 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
470 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
472 // jq = (cv ? jq : 0);
473 jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
474 DAG.getConstant(0, OVT));
476 iq = DAG.getSExtOrTrunc(iq, DL, OVT);
477 iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
482 AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
483 DebugLoc DL = Op.getDebugLoc();
484 EVT OVT = Op.getValueType();
485 SDValue LHS = Op.getOperand(0);
486 SDValue RHS = Op.getOperand(1);
487 // The LowerSDIV32 function generates equivalent to the following IL.
497 // ixor r10, r10, r11
508 SDValue r10 = DAG.getSelectCC(DL,
509 r0, DAG.getConstant(0, OVT),
510 DAG.getConstant(-1, MVT::i32),
511 DAG.getConstant(0, MVT::i32),
515 SDValue r11 = DAG.getSelectCC(DL,
516 r1, DAG.getConstant(0, OVT),
517 DAG.getConstant(-1, MVT::i32),
518 DAG.getConstant(0, MVT::i32),
522 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
525 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
528 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
531 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
534 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
536 // ixor r10, r10, r11
537 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
540 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
543 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
548 AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
549 return SDValue(Op.getNode(), 0);
553 AMDGPUTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const {
554 DebugLoc DL = Op.getDebugLoc();
555 EVT OVT = Op.getValueType();
556 MVT INTTY = MVT::i32;
557 if (OVT == MVT::v2i8) {
559 } else if (OVT == MVT::v4i8) {
562 SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
563 SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
564 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
565 LHS = DAG.getSExtOrTrunc(LHS, DL, OVT);
570 AMDGPUTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const {
571 DebugLoc DL = Op.getDebugLoc();
572 EVT OVT = Op.getValueType();
573 MVT INTTY = MVT::i32;
574 if (OVT == MVT::v2i16) {
576 } else if (OVT == MVT::v4i16) {
579 SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
580 SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
581 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
582 LHS = DAG.getSExtOrTrunc(LHS, DL, OVT);
587 AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
588 DebugLoc DL = Op.getDebugLoc();
589 EVT OVT = Op.getValueType();
590 SDValue LHS = Op.getOperand(0);
591 SDValue RHS = Op.getOperand(1);
592 // The LowerSREM32 function generates equivalent to the following IL.
614 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
617 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
620 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
623 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
626 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
629 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
632 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
635 r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
638 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
641 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
644 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
649 AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
650 return SDValue(Op.getNode(), 0);